MT48H32M16LFCJ-75 Micron Technology Inc, MT48H32M16LFCJ-75 Datasheet - Page 35

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MT48H32M16LFCJ-75

Manufacturer Part Number
MT48H32M16LFCJ-75
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48H32M16LFCJ-75

Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
9/6ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
90mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant

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Figure 26:
Deep Power-Down
Figure 27:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
Power-Down
Deep Power-Down Command
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting
COMMAND
Deep power-down mode is a maximum power savings feature achieved by shutting off
the power to the entire memory array of the device. Data on the memory array will not
be retained once deep power-down mode is executed. Deep power-down mode is
entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH
at the rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep
power-down.
BA0, BA1
CKE
CLK
A0–A12
All banks idle
RAS#
CAS#
WE#
Enter power-down mode.
CK#
CKE
CS#
CK
t CKS
NOP
DON’T CARE
Input buffers gated off
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
35
(
(
(
(
)
(
)
)
)
)
(
(
(
(
)
(
)
)
)
)
Exit power-down mode.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CKS). See Figure 28 on page 36.
> t CKS
NOP
DON’T CARE
©2005 Micron Technology, Inc. All rights reserved.
ACTIVE
t RCD
t RAS
t RC
Operations

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