MT46V16M8P-75 Micron Technology Inc, MT46V16M8P-75 Datasheet - Page 44

• Manufacturer Part Number: MT46V16M8P-75
• Manufacturer: Micron Technology Inc

Specifications of MT46V16M8P-75

• Lead Free Status / Rohs Status: Compliant

Figure 20:
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
COMMAND
ADDRESS
BA0, BA1
V
V
DQS
V
CK#
CKE
A10
DD
DM
V
DQ
CK
TT
REF
DD
Q
1
t VTD 1
INITIALIZATION Timing Diagram
Notes:
LVCMOS
LOW LEVEL
T = 200µs
Power-up: V
1. V
2. Although not required by the Micron device, JEDEC specifies issuing another LMR command
3. The two AUTO REFRESH commands at Td0 and Te0 may be applied following the LOAD
4.
5. While programming the operating parameters, reset the DLL with A8 = 1.
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DD
V
even if V
between the V
within the specified range.
(A8 = 0) prior to activating any bank. If another LMR command is issued, the same, previ-
ously issued operating parameters must be used.
MODE REGISTER (LMR) command at Ta0.
t
DESELECTs are allowed), and 200 cycles of CK are required before a READ command can be
issued.
MRD is required before any command can be applied (during MRD time only NOPs or
and CK stable
TT
TT
t IS
t
IS
NOP
T0
, and V
is not applied directly to the device; however,
High-Z
High-Z
t IH
t
t
IH
CH
t
CK
DD
REF
t
/V
CL
ALL BANKS
t IS
DD
≤ V
PRE
T1
TT
Q are 0V, provided a minimum of 42 ohms of series resistance is used
t IH
DD
supply and the input pin. Once initialized, V
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+ 0.3V. Alternatively, V
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t RP
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Load extended
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mode register
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t IS
t IS
t IS
BA0 = 1
BA1 = 0
CODE
CODE
LMR
Ta0
t IH
t IH
t IH
44
t MRD
dc
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Load mode
register 5
BA0 = 0
BA1 = 0
CODE
CODE
LMR
Tb0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
t MRD
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TT
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ALL BANKS
may be 1.35V maximum during power up,
t
IS
128Mb: x4, x8, x16 DDR SDRAM
Tc0
PRE
t
IH
t
VTD ≥ 0 to avoid device latch-up. V
t RP
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200 cycles of CK
Td0
AR
REF
t RFC
©2004 Micron Technology, Inc. All rights reserved.
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must always be powered
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4
Te0
AR
t RFC
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Operations
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ACT
Tf0
RA
DON’T CARE
RA
BA
2
DD
Q,