ADV612BST Analog Devices Inc, ADV612BST Datasheet - Page 21

• Manufacturer Part Number: ADV612BST
• Manufacturer: Analog Devices Inc

Specifications of ADV612BST

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / Rohs Status: Compliant

Video Interface
The ADV611/ADV612 video interface supports two types of
component digital video (D1) interfaces in both compression
(input) and decompression (output) modes. These digital video
interfaces include support for the Multiplexed Philips 4:2:2 and
CCIR-656/SMPTE125M—international standard.
Video interface master and slave modes allow for the generation or
receiving of synchronization and blanking signals. Definitions for
the different formats can be found later in this section. For recom-
mended connections to popular video decoders and encoders, see
the Connecting the ADV611/ADV612 to Popular Video Decoders
and Encoders section. A complete list of supported video interfaces
and sampling rates is included in Table VI.
Name
CCIR-656
Multiplex
Internally, the video interface translates all video formats to one
consistent format to be passed to the wavelet kernel. This con-
sistent internal video standard is 4:2:2 at 16 bits accuracy.
VITC and Closed Captioning Support
The video interface also supports the direct loss-less extraction
of 90-bit VITC codes during encode and the insertion of VITC
codes during decode. Closed Captioning data (found on active
Video Line 21) is handled just as normal active video on an
active scan line. As a result, no special dedicated support is
necessary for Closed Captioning. The data rates for Closed
Captioning data are low enough to ensure robust operation of
this mechanism at compression ratios of 50:1 and higher. Note
that you must include Video Line 21 in the ADV611/ADV612’s
defined active video area for Closed Caption support.
27 MHz Nominal Sampling
There is one clock input (VCLK) to support all internal process-
ing elements. This is a 50% duty cycle signal and must be syn-
chronous to the video data. Internally this clock is doubled using
a phase locked loop to provide for a 54 MHz internal processing
clock. The clock interface is a two pin interface that allows a
crystal oscillator to be tied across the pins or a clock oscillator to
drive one pin. The nominal clock rate for the video interface is
27 MHz. Note that the ADV611/ADV612 also supports a pixel
rate of 13.5 MHz.
Video Interface and Modes
In all, there are seven programmable features that configure the
video interface. These are:
• Encode-Decode Control
REV. 0
Philips
In addition to determining what functions the internal pro-
cessing elements must perform, this control determines the
direction of the video interface. In decode mode, the video
interface outputs data. In encode mode, the interface receives
data. The state of the control is reflected on the ENC pin.
This pin can be used as an enable input by external line driv-
ers. This control is maintained by the host processor.
Table VI. Component Digital Video Interfaces
Bits/
Component Space
8
8
Color
YCrCb 4:2:2
YUV
Sampling Rate (MHz) I/F Width
4:2:2
Nominal
Date
27
27
8
8
–21–
• Master-Slave Control
• 525-625 (NTSC-PAL) Control
525-625
Control
0
1
• Bipolar/Unipolar Color Component
• Active Area Control
• Video Format
This control determines whether the ADV611/ADV612 gen-
erates or receives the VSYNC, HSYNC, and FIELD signals.
In master mode, the ADV611/ADV612 generates these sig-
nals for external hardware synchronization. In slave mode, the
ADV611/ADV612 receives these signals. Note that some video
formats require the ADV611/ADV612 to operate in slave mode
only. This control is maintained by the host processor.
This control determines whether the ADV611/ADV612 is
operating on 525/NTSC video or 625/PAL video. This infor-
mation is used when the ADV611/ADV612 is in master and
decode modes so that the ADV611/ADV612 knows where
and when to generate the HSYNC, VSYNC, and FIELD
Pulses as well as when to insert the SAV and EAV time codes
(for CCIR-656 only) in the data stream. This control is main-
tained by the host processor. Table VII shows how the 525-
625 Control in the Mode Control register works.
This mode determines whether offsets are used on color com-
ponents. In Philips mode, this control is usually set to Bipo-
lar, since the color components are normal twos-compliment
signed values. In CCIR-656 mode, this control is set to Uni-
polar, since the color components are offset by 128. Note that
it is likely the ADV611/ADV612 will function if this control is
in the wrong state, but compression performance will be
degraded. It is important to set this bit correctly.
Four registers HSTART (horizontal start), HEND (horizon-
tal end), VSTART (vertical start) and VEND (vertical end)
determine the active video area. The maximum active video
area is 720 by 288 pixels for a single field.
This control determines the video format that is supported. In
general, the goal of the various video formats is to support
glueless interfaces to the wide variety of video formats periph-
eral components expect. This control is maintained by the
host processor. Table VIII shows a synopsis of the supported
video formats. Definitions of each format can be found later
in this section. For Video Interface pins descriptions, see the
Pin Function Descriptions.
Table VII. Square Pixel Control, 525-625 Control, and
Video Formats
Max
Horizontal
Size
720
720
ADV611/ADV612
Max
Field
Size
243
288
NTSC-PAL
CCIR-601 NTSC
CCIR-601 PAL