CY22E016L-SZ25XC Cypress Semiconductor Corp, CY22E016L-SZ25XC Datasheet - Page 3

• Manufacturer Part Number: CY22E016L-SZ25XC
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of CY22E016L-SZ25XC

• Word Size: 8b
• Organization: 2Kx8
• Density: 16Kb
• Interface Type: Parallel
• Access Time (max): 25ns
• Operating Supply Voltage (typ): 5V
• Package Type: SOIC
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Pin Count: 28
• Mounting: Surface Mount
• Supply Current: 85mA
• Lead Free Status / Rohs Status: Compliant

Device Operation
The CY22E016L nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables storage and recall
of all cells in parallel. During the STORE and RECALL opera-
tions, SRAM READ and WRITE operations are inhibited. The
CY22E016L supports infinite reads and writes similar to a typical
SRAM. In addition, it provides infinite RECALL operations from
the nonvolatile cells and up to one million STORE operations.
SRAM Read
The CY22E016L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
accessed. When the READ is initiated by an address transition,
the outputs are valid after a delay of t
READ is initiated by CE or OE, the outputs are valid at t
t
repeatedly respond to address changes within the t
time without the need for transitions on any control input pins,
and remains valid until another address change or until CE or OE
is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs are stable prior to entering the
WRITE cycle and must remain stable until either CE or WE goes
HIGH at the end of the cycle. The data on the common IO pins
IO
of a WE controlled WRITE or before the end of an CE controlled
WRITE. Keep OE HIGH during the entire WRITE cycle to avoid
data bus contention on common IO lines. If OE is left LOW,
internal circuitry turns off the output buffers t
LOW.
AutoStore Operation
During normal AutoStore operation, the CY22E016L draws
current from V
pin. This stored charge is used by the chip to perform a single
STORE operation. After power up, when the voltage on the V
pin drops below V
V
Figure 1
(V
having a capacity of between 68 μF and 220 μF (±20%) rated at
6V, is provided. In system power mode, both V
connected to the +5V power supply without the 68 μF capacitor.
In this mode, the AutoStore function of the CY22E016L operates
Document Number: 001-06727 Rev. *E
DOE
CAP
CAP
0–7
, whichever is later (READ cycle 2). The data outputs
pin from V
) for automatic store operation. A charge storage capacitor,
is written into the memory if it is valid t
shows the proper connection of the storage capacitor
0–10
CC
determines which of the 2,048 data bytes are
CC
SWITCH
to charge a capacitor connected to the V
and initiates a STORE operation.
, the part automatically disconnects the
AA
(READ cycle 1). If the
HZWE
SD,
CC
before the end
after WE goes
and V
AA
ACE
CAP
access
or at
CAP
CAP
are
on the stored system charge as power goes down. The user
must, however, guarantee that V
during the 10 ms STORE cycle..
Figure 1. AutoStore Mode
Figure 2. System Power Mode
1
14
14
1
28
27
26
28
26
15
27
15
CC
does not drop below 3.6V
CY22E016L
Page 3 of 14
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