SC16C850VIBS-F NXP Semiconductors, SC16C850VIBS-F Datasheet
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SC16C850VIBS-F
Specifications of SC16C850VIBS-F
Related parts for SC16C850VIBS-F
SC16C850VIBS-F Summary of contents
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SC16C850V 1.8 V single UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface Rev. 5 — 19 January 2011 1. General description The SC16C850V is a 1.8 V, low power single channel Universal Asynchronous Receiver ...
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... Independent transmitter and receiver enable/disable Pb-free, RoHS compliant package offered 3. Ordering information Table 1. Type number SC16C850VIBS HVQFN32 plastic thermal enhanced very thin quad flat package; SC16C850V Product data sheet Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Ordering information ...
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... NXP Semiconductors 4. Block diagram SC16C850V AD0 to AD7 IOR IOW RESET LLA CS LOWPWR INTERRUPT INT Fig 1. Block diagram of SC16C850V SC16C850V Product data sheet Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface DATA BUS AND CONTROL LOGIC REGISTER SELECT LOGIC ...
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... Product data sheet Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface terminal 1 index area AD4 1 n. AD5 4 AD6 SC16C850VIBS AD7 Transparent top view Pin configuration for HVQFN32 All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 January 2011 ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin Type Description INT 20 O Interrupt output. The output state is defined by the user through the software setting of MCR[5]. INT is set to the active mode when MCR[5] is set to a logic 0. INT is set to the open-source mode when MCR[3] is set to a logic 1. See ...
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... NXP Semiconductors 6. Functional description The SC16C850V provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol) ...
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... NXP Semiconductors 6.2 Extended mode (128-byte FIFO) The device is in the extended mode when any of these four registers contains any value other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL. 6.3 Internal registers The SC16C850V provides a set of 25 internal registers for monitoring and controlling the functions of the UART ...
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... NXP Semiconductors [3] Second special registers are accessible only when EFCR[ [4] Enhanced Feature Registers are only accessible when LCR = 0xBF. [5] First extra feature registers are only accessible when EFCR[2:1] = 01b. [6] Second extra feature registers are only accessible when EFCR[2:1] = 10b. 6.4 FIFO operation 6 ...
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... NXP Semiconductors When AFCR1[2] is set to 1, then the function of CTS pin is mapped to the DSR pin, and the function of RTS is mapped to DTR pin. DSR and DTR pins will behave as described above for CTS and RTS. With the automatic hardware flow control function enabled, an interrupt is generated when the receive FIFO reaches the programmed trigger level ...
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... NXP Semiconductors In the event that the receive buffer is overfilling, the SC16C850V automatically sends an Xoff character (when enabled) via the serial TX output to the remote UART. The SC16C850V sends the Xoff1/Xoff2 characters as soon as the number of received data in the receive FIFO passes the programmed trigger level. To clear this condition, the SC16C850V will transmit the programmed Xon1/Xon2 characters as soon as the number of characters in the receive FIFO drops below the programmed trigger level ...
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... NXP Semiconductors 6.9 Programmable baud rate generator The SC16C850V UART contains a programmable rational baud rate generator that takes any clock input and divides divisor in the range between 1 and (2 SC16C850V offers the capability of dividing the input frequency by rational divisor. The fractional part of the divisor is controlled by the CLKPRES register in the First Extra Register Set ...
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... NXP Semiconductors Fig 4. Fig 5. Table 6. Output baud rate (bit/ 110 150 300 600 1.2 k 2.4 k 3.6 k 4.8 k 7.2 k 9.6 k 19.2 k 38.4 k 57.6 k 115.2 k SC16C850V Product data sheet Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface XTAL1 XTAL2 X1 1.8432 MHz ...
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... NXP Semiconductors 6.10 Loopback mode The internal loopback capability allows on-board diagnostics. In the Loopback mode, the normal modem interface pins are disconnected and reconfigured for loopback internally (see Figure In the Loopback mode, the transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally ...
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... NXP Semiconductors SC16C850V AD0 to AD7 DATA BUS IOR AND IOW CONTROL RESET LOGIC LLA REGISTER CS SELECT LOGIC POWER DOWN LOWPWR CONTROL INTERRUPT INT CONTROL LOGIC Fig 6. Internal Loopback mode diagram SC16C850V Product data sheet Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface ...
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... NXP Semiconductors 6.11 Sleep mode Sleep mode is an enhanced feature of the SC16C850V UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] bit is also set. 6.11.1 Conditions to enter Sleep mode Sleep mode is entered when: • Modem input pins are not toggling. ...
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... NXP Semiconductors 6.13 RS-485 Features 6.13.1 Auto RS-485 RTS control Normally the RTS pin is controlled by MCR bit hardware flow control is enabled, the logic state of the RTS pin is controlled by the hardware flow control circuitry. EFCR2 register bit 4 will take the precedence over the other two modes; once this bit is set, the transmitter will control the state of the RTS pin ...
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... NXP Semiconductors 6.13.3.2 Auto address detection If Special Character Detect is enabled (EFR[5] is set and the Xoff2 register contains the address byte), the receiver will try to detect an address byte that matches the programmed character in the Xoff2 register. If the received byte is a data byte or an address byte that does not match the programmed character in the Xoff2 register, the receiver will discard these data ...
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Table 7. SC16C850V internal registers [ Register Default Bit 7 [2] General Register Set RHR XX bit THR XX bit IER 00 CTS interrupt 0 1 ...
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Table 7. SC16C850V internal registers …continued [ Register Default Bit 7 [6] Enhanced Register Set EFR 00 Auto CTS Xon1 00 bit Xon2 00 bit 15 1 ...
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... NXP Semiconductors 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (AD7 to AD0) to the transmit FIFO ...
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... NXP Semiconductors Table 8. Bit Symbol Description 1 IER[1] 0 IER[0] 7.2.1 IER versus transmit/receive FIFO interrupt mode operation When the receive FIFO is enabled (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • ...
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... NXP Semiconductors 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs and set the receive FIFO trigger levels. 7.3.1 FIFO mode Table 9. Bit 7:6 5 [1] For 128-byte FIFO mode, refer to [2] For 128-byte FIFO mode, refer to Table 10 ...
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... NXP Semiconductors Table 11. FCR[ [1] When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and transmit trigger levels are set by RXINTLVL, TXINTLVL; see 7.4 Interrupt Status Register (ISR) The SC16C850V provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits ...
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... NXP Semiconductors Table 13. Bit 0 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 14. Bit 7 6 5:3 ...
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... NXP Semiconductors Table 17. LCR[ 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 18. Bit Symbol 7 MCR[7] 6 MCR[6] 5 MCR[5] 4 MCR[4] 3 MCR[3] 2 MCR[2] 1 MCR[1] 0 MCR[0] SC16C850V Product data sheet Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface ...
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... NXP Semiconductors Table 19. MCR[ 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C850V and the CPU. Table 20. Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] SC16C850V Product data sheet Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface ...
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... NXP Semiconductors Table 20. Bit Symbol 0 LSR[0] 7.8 Modem Status Register (MSR) This register shares the same address as EFCR register. This is a read-only register and it provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C850V is connected. Four bits of this register are used to indicate the changed information ...
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... NXP Semiconductors 7.9 Extra Feature Control Register (EFCR) This is a write-only register, and it allows the software access to these registers: First Extra Register Set, Second Extra Register Set, Transmit FIFO Level Counter (TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT). Table 22. Bit 7:3 ...
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... NXP Semiconductors 7.14 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bit 0 through bit 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential numbers ...
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... NXP Semiconductors Table 24. Cont [1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer. 7.15 Transmit Interrupt Level register (TXINTLVL) This 8-bit register is used store the transmit FIFO trigger levels used for interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1. ...
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... NXP Semiconductors [1] For 32-byte FIFO mode, refer to 7.17 Flow Control Trigger Level High (FLWCNTH) This 8-bit register is used to store the receive FIFO high threshold levels to start/stop transmission during hardware/software flow control. register bit settings; see Table 27. Bit 7:0 [1] For 32-byte FIFO mode, refer to 7 ...
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... NXP Semiconductors 7.20 RS-485 turn-around time delay (RS485TIME) The value in this register controls the turn-around time of the external line transceiver in bit time. In automatic 9-bit mode, the RTS or DTR pin is used to control the direction of the line driver, after the last bit of data has been shifted out of the transmit shift register the UART will count down the value in this register ...
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... NXP Semiconductors 7.22 Advanced Feature Control Register 2 (AFCR2) Table 32. Bit 7 SC16C850V Product data sheet Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Advanced Feature Control Register 2 bits description Symbol Description AFCR2[7:6] reserved AFCR2[5] RTSInvert. Invert RTS or DTR signal in auto 9-bit mode. ...
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... NXP Semiconductors 7.23 SC16C850V external reset condition and software reset These two reset methods are identical and will reset the internal registers as indicated in Table 33. Table 33. Register IER FCR ISR LCR MCR LSR MSR EFCR SPR DLL DLM TXLVLCNT RXLVLCNT EFR Xon1 ...
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... NXP Semiconductors 8. Limiting values Table 35. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol amb T stg P /pack total power dissipation per tot [1] V should not exceed 2 Static characteristics Table 36. − amb Symbol V IL(clk) V IH(clk LIL I LIH I L(clk DD(sleep) I DD(lp) ...
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... NXP Semiconductors 10. Dynamic characteristics Table 37. Dynamic characteristics − ° ° + 1. 1.95 V; unless otherwise specified. amb DD Symbol Parameter f frequency on pin XTAL1 XTAL1 t delay time from CS to LLA HIGH d(CS-LLAH) t set-up time from address to LLA HIGH su(A-LLAH) t LLA pulse width time w(LLA) t address hold time after LLA HIGH ...
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... NXP Semiconductors 10.1 Timing diagrams AD7 to AD0 CS LLA IOW Fig 7. General write timing AD7 to AD0 CS LLA IOR Fig 8. General read timing SC16C850V Product data sheet Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface upper address lower address t su(A-LLAH) ...
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... NXP Semiconductors IOW RTS change of state DTR CD CTS DSR INT IOR RI Fig 9. Modem input/output timing external clock -------------- - XTAL1 clk Fig 10. External clock timing SC16C850V Product data sheet Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface active t d(IOW-Q) change of state ...
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... NXP Semiconductors RX INT IOR Fig 11. Receive timing TX INT active IOW Fig 12. Transmit timing SC16C850V Product data sheet Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface start bit data bits ( data bits 6 data bits 7 data bits 16 baud rate clock ...
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... NXP Semiconductors IrDA TX data Fig 13. Infrared transmit timing IrDA RX data RX data Fig 14. Infrared receive timing SC16C850V Product data sheet Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface start TX data bit time bit time start All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 11. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 16. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 13. Abbreviations Table 40. Acronym CPU FIFO IrDA ISDN LSB MSB RoHS UART VLIO SC16C850V Product data sheet ...
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... NXP Semiconductors 14. Revision history Table 41. Revision history Document ID Release date SC16C850V v.5 20110119 • Modifications: Table 36 “Static – V IL(clk) – V IH(clk) – – – Added (new) SC16C850V v.4 20080114 SC16C850V v.3 20070924 SC16C850V v.2 20070413 SC16C850V v.1 20061107 SC16C850V Product data sheet ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 UART selection 6.2 Extended mode (128-byte FIFO 6.3 Internal registers . . . . . . . . . . . . . . . . . . . . . . . . 7 6.4 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.4.1 32-byte FIFO mode ...