W9825G6DH-6I Winbond Electronics, W9825G6DH-6I Datasheet - Page 5

• Manufacturer Part Number: W9825G6DH-6I
• Manufacturer: Winbond Electronics
• Type: SDRAMr

Specifications of W9825G6DH-6I

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 6/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

5. PIN DESCRIPTION
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
45, 47, 48, 50,
PIN NUMBER
6, 12, 46, 52
3, 9, 43, 49
23−26, 22,
28, 41, 54
1, 14, 27
29−36
20, 21
51, 53
15, 39
19
18
17
16
38
37
40
DQ0−DQ15
PIN NAME
BS0, BS1
A0−A12
LDQM,
UDQM
V
V
RAS
CAS
CKE
CLK
V
WE
V
NC
CS
CCQ
SSQ
CC
SS
No Connection
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Power (+3.3V)
Row Address
Clock Enable
Write Enable Referred to RAS
for I/O Buffer
for I/O Buffer
Input/Output
Input/Output
Clock Inputs
Bank Select
Chip Select
FUNCTION
Address
Address
Column
Ground
Ground
Strobe
Strobe
Mask
Data
Multiplexed pins for row and column address.
Row address: A0−A12. Column address: A0−A8.
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock, RAS , CAS and WE define the operation
to be executed.
Referred to RAS
The output buffer is placed at Hi-Z(with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write operation
with zero latency.
System clock used to sample inputs on the rising edge
of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend mode,
or Self Refresh mode is entered.
Ground for input buffers and logic circuit inside DRAM.
Separated power from V
immunity.
Separated ground from V
immunity.
No connection. (NC pin should be connected to GND
or floating)
- 5 -
Publication Release Date:Apr. 24, 2008
DESCRIPTION
CC
SS
, to improve DQ noise
, to improve DQ noise
W9825G6DH
Revision A12