IDT49C466PQF IDT, Integrated Device Technology Inc, IDT49C466PQF Datasheet - Page 10

• Manufacturer Part Number: IDT49C466PQF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT49C466PQF

• Lead Free Status / Rohs Status: Not Compliant

OPERATING MODE DESCRIPTION
Memory Initialization
to checkbit memory. This can be done using the 49C466 to first create an "all-zero-data" source. This is done by setting the CLEAR bit in the mode register.
This clears all diagnostic registers. Then this data can be written back to memory in the Error-Data output (Mode 0) mode. In order to wrap the all-zero data
back to the MD bus, BE0-7 should be high and WBSEL =0.
Partial Word Write/Byte Merge
case. The checkbits generated for a data word shorter than 64 bits and
written to a particular memory location differ from the checkbits that would
be generated by the entire 64-bit data word at the same location. Hence,
the byte merge operation requires reading of the contents of the memory
location to be written to, merging the byte/bytes being written (from SD side)
with the other component bytes previously at that memory location (from MD
side), generating a checkbit word for this composite word and writing both
the composite data word and the generated checkbits to memory. The BEn
bits supplied by the user determine the bytes that come from SD and those
that come from MD, as illustrated in Figure 1.
EDC Modes
Mode Description table for a description of the modes.
described below. In Checkbit Injection mode, the MD Checkbit Latch
is loaded with data from the System Bus. This serves to verify the functioning
of the EDC. Any discrepancy between the injected checkbits and generated
checkbits should result in assertion of the ERR, MERR signals.
ration, etc., can be selected by appropriately loading the Mode Register.
The Mode Register can be written to by asserting MEN. Then SD
clocked into the mode register on the rising edge of SCLK.
IDT49C466, IDT49C466A
64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MODE 0
MODE 1
MODE 2
MODE 3
MODE 4
Memory initialization involves clearing all memory data locations and writing the corresponding checkbits (checkbits corresponding to all zero data = $0C)
Writing a word shorter than 64 bits to memory is treated as a special
The IDT49C466 has five modes of operation. Refer to the Operating
The Error Data Output mode is useful for memory initialization as
These modes and certain other features such as clear, buffer configu-
Mode
Error-Data Output Mode: This mode allows the uncorrected data captured from an error event by the Error-Data Register to be read by the
system for diagnostic purposes. The Error-Data Register is cleared by setting the mode register "'clear"-bit.
Diagnostic-Output Mode: In this mode, contents of latch and five internal registers are read by the system for diagnostic and error logging
purposes. Internal data paths allow output from the CBI LATCH to be read directly by the system bus for diagnostic purposes. The contents of
the internal diagnostic checkbit register, syndrome registers, error count register and error-type register are also output on the SD bus.
Generate-Detect Mode: (Detect-Only) The EDC performs checkbit generation during a memory write, and performs error detection only during a
memory read.
Normal Mode: The EDC performs checkbit generation during memory writes and error detection and correction during memory reads.
Checkbit-Injection Mode: In this mode, the checkbit latch is loaded with desired 8-bit data from the SD bus.This eight bit data passes through
SD Latch in or write FIFO to the MD check bit latch. By inserting various checkbit values, correct functioning of the EDC can be verified “on-
board”. The rest of the operation is similar to regular memory reads. The EDC compares the injected checkbits against the internally generated
checkbits. Any discrepancy in the injected checkbits and the internally generated checkbits will cause the ERR / MERR to go LOW.
0-15
Description
is
10
MODE REGISTER CONFIGURATION
EDC M 2
15
CLE AR
UNU SE D
0
0
0
0
1
RW B D
CLEAR
RM O DE
PS EL
EDC M 1 EDCM 0
0
1
0
1
0
1
0
1
0
0
1
1
0
7
RM O DE
6
0
1
0
1
0
PSEL
COMMERCIAL TEMPERATURE RANGE
5
SINGLE FIFO (16)
ERRO R-DATA O UTPU T M O DE
DIAGN O STIC-OUTPUT M O DE
GENE RATE-D ETEC T M O DE
NO RM AL M OD E
CHECKBIT-INJECTIO N M O DE
READ M O DE REG ISTER O N S D B US
DUAL FIFO S (8)
OD D PAR ITY
CLEA R A LL D IAG NOS TIC REG ISTERS
EVE N PAR ITY
RW BD
4
NOP
NO P
O PER ATION
O PER ATION
O PER ATIO N
O PER ATIO N
OPERATIO N
CLEAR
3
2
EDC M 0-2
0