IDT49C466PQF IDT, Integrated Device Technology Inc, IDT49C466PQF Datasheet - Page 7

• Manufacturer Part Number: IDT49C466PQF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT49C466PQF

• Lead Free Status / Rohs Status: Not Compliant

DETAILED DESCRIPTION —
64-BIT SYNDROME DECODE TO BIT-IN-ERROR
NOTES:
1. The table indicates the decoding of the eight syndrome bits to identify the bit-in-error for a single-bit error, or whether a double or triple-bit error was
IDT49C466 OPERATION
memory writes. With the IDT49C466, both these can be accomplished by
utilizing either of two possible data paths — one incorporating the FIFO and
the other without the FIFO. These operations are treated separately below.
Memory Write
since it does not call for any error checking. It only generates the check
bits associated with each 64-bit wide data word. The EDC can be in
generate-detect or normal mode for this operation.
output buffer (enabled by SOE and BE
made to simultaneously transfer read data onto the System Data (SD) Bus.
through the SD Latch In. To latch data, the SDILE signal should be pulled
LOW. The special case of a partial word write or byte merge is discussed
IDT49C466, IDT49C466A
64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
detected. The all-zero case indicates no error detected.
* = No errors detected
# = The number of the single data bit-in-error
T = Two errors detected
M = Three or more detected
C# = The number of the single checkbits in error
HEX
The EDC is involved in two types of operation — memory reads and
The involvement of the EDC in this type of operation is relatively minimal
When a write operation is performed, it must be ensured that the SD
When the write FIFO (WFIFO) is bypassed (WBSEL LOW), data passes
C
A
B
D
E
0
1
2
3
4
5
6
7
8
9
F
S3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Syndrome
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bits
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEX
S7
S6
S5
S4
0-7
) is disabled so that no attempt is
C0
C1
C2
C3
M
17
M
16
0
0
0
0
0
*
T
T
T
T
T
T
T
(1)
C4
18
19
20
21
22
23
M
1
0
0
0
1
T
T
T
T
T
T
T
T
C5
10
11
12
13
M
2
0
0
1
0
T
T
8
T
9
T
T
T
T
T
14
M
15
M
M
M
M
M
3
0
0
1
1
T
T
T
T
T
T
T
T
C6
33
32
M
M
M
M
M
4
0
1
0
0
T
T
T
T
T
T
T
T
7
later. Here it is assumed that all 64 bits are being written. Consequently,
BE
checkbits are generated. Both system data and the generated checkbits
can be latched by pulling the SDOLE signal HIGH. Asserting MOE enables
the MD output buffer and data is output to the Memory Data (MD) bus.
CBSEL (=1) or MOE(=0) need to be asserted to enable the CBSYN output
buffer and output checkbits on CBSYN
SDILE, WBEN is asserted and data is clocked into the write FIFO on the
rising edge of SCLK. WBFF is asserted when the WFIFO is full and this
inhibits further write attempts (see section on "Clock Skew" and "R/W FIFO
Operation at Boundaries") to the WFIFO. When WBREN is asserted, data
can be clocked out of the write FIFO on the rising edge of MCLK. WBEF
is asserted when the WFIFO is empty and this inhibits further read attempts
(see section on "Clock Skew") from the WFIFO.
M
34
35
36
37
38
39
M
5
0
1
0
1
T
T
T
T
T
T
T
T
0-7
The data is fed to the SD Checkbit generator where appropriate
When the write FIFO is selected (WBSEL = 1), instead of asserting
must all be LOW.
56
57
58
59
60
61
M
M
6
0
1
1
0
T
T
T
T
T
T
T
T
62
63
M
M
M
M
M
M
7
0
1
1
1
T
T
T
T
T
T
T
T
C7
M
M
M
M
49
M
48
8
1
0
0
0
T
T
T
T
T
T
T
T
50
51
52
53
54
55
M
M
COMMERCIAL TEMPERATURE RANGE
9
1
0
0
1
T
T
T
T
T
T
T
T
40
41
42
43
44
45
M
M
A
1
0
1
0
T
T
T
T
T
T
T
T
0-7
.
46
M
47
M
M
M
M
M
B
1
0
1
1
T
T
T
T
T
T
T
T
C
M
M
M
M
M
M
1
1
0
0
T
T
T
T
T
T
1
T
0
T
M
M
D
1
1
0
1
T
T
2
T
3
4
T
T
5
6
T
7
T
T
24
25
26
27
28
M
29
M
E
1
1
1
0
T
T
T
T
T
T
T
T
30
31
M
M
M
M
M
M
F
1
1
1
1
T
T
T
T
T
T
T
T