M25PX16-VMW6G Micron Technology Inc, M25PX16-VMW6G Datasheet - Page 15

• Manufacturer Part Number: M25PX16-VMW6G
• Manufacturer: Micron Technology Inc

Specifications of M25PX16-VMW6G

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SO W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

4.7.1
4.7.2
Protocol-related protections
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25PX16 features the following data protection mechanisms:
Specific hardware and software protection
There are two software protected modes, SPM1 and SPM2, that can be combined to protect
the memory array as required. The SPM2 can be locked by hardware with the help of the W
input pin.
SPM1 and SPM2
Power On Reset and an internal timer (t
inadvertent changes while the power supply is outside the operating specification
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
–
–
–
–
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection, as all Write, Program and Erase instructions are ignored.
The first software protected mode (SPM1) is managed by specific Lock Registers
assigned to each 64 Kbyte sector.
The Lock Registers can be read and written using the Read Lock Register (RDLR) and
Write to Lock Register (WRLR) instructions.
In each Lock Register two bits control the protection of each sector: the Write Lock bit
and the Lock Down bit.
–
–
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write to Lock Register (WRLR) instruction completion
Program OTP (POTP) instruction completion
Page Program (PP) instruction completion
Dual Input Fast Program (DIFP) instruction completion
Subsector Erase (SSE) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Write Lock bit:
The Write Lock bit determines whether the contents of the sector can be modified
(using the Write, Program or Erase instructions). When the Write Lock bit is set to
‘1’, the sector is write protected – any operations that attempt to change the data
in the sector will fail. When the Write Lock bit is reset to ‘0’, the sector is not write
protected by the Lock Register, and may be modified.
Lock Down bit:
The Lock Down bit provides a mechanism for protecting software data from simple
hacking and malicious attack. When the Lock Down bit is set, ‘1’, further
PUW
) can provide protection against
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