M28W640HCT70N6E NUMONYX, M28W640HCT70N6E Datasheet - Page 12

• Manufacturer Part Number: M28W640HCT70N6E
• Description: TSOP-1 48 12X20 CUSTD FLASH
• Manufacturer: NUMONYX

Signal descriptions
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2.1
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2.3
2.4
2.5
2.6
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Signal descriptions
See
connected to this device.
Address inputs (A0-A21)
The Address inputs select the cells in the memory array to access during bus read
operations. During bus write operations they control the commands sent to the command
interface of the internal state machine.
Data input/output (DQ0-DQ15)
The Data I/O outputs the data stored at the selected address during a bus read operation or
inputs a command or the data to be programmed during a write bus operation.
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at V
mode. When Chip Enable is at V
impedance and the power consumption is reduced to the standby level.
Output Enable (G)
The Output Enable controls data outputs during the bus read operation of the memory.
Write Enable (W)
The Write Enable controls the bus write operation of the memory’s command interface. The
data and address inputs are latched on the rising edge of Chip Enable, E, or Write Enable,
W, whichever occurs first.
Write Protect (WP)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is at V
cannot be changed. When Write Protect is at V
can be locked or unlocked (refer to
Figure 1: Logic diagram
IL
, the lock-down is enabled and the protection status of the block
and
IH
Table 1: Signal
the memory is deselected, the outputs are high
Table 7: Read Protection Register and Lock
IL
and Reset is at V
IH
names, for a brief overview of the signals
, the lock-down is disabled and the block
M28W640HCT, M28W640HCB
IH
the device is in active
Register).