LFEC3E-3F256I Lattice, LFEC3E-3F256I Datasheet - Page 63

• Manufacturer Part Number: LFEC3E-3F256I
• Description: FPGA LatticeEC Family 3100 Cells 340MHz 130nm (CMOS) Technology 1.2V 256-Pin FBGA
• Manufacturer: Lattice

Specifications of LFEC3E-3F256I

• Package: 256FBGA
• Family Name: LatticeEC
• Device Logic Units: 3100
• Maximum Internal Frequency: 340 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 160
• Ram Bits: 56320
• In System Programmability: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Figure 3-14. sysCONFIG Master Serial Port Timing
Figure 3-15. sysCONFIG Slave Serial Port Timing
Figure 3-16. Power-On-Reset (POR) Timing
CCLK (output)
CCLK (input)
V
1. Time taken from V
2. Device is in a Master Mode.
3. The CFG pins are normally static (hard wired).
CC
/V
CFG[2:0]
DOUT
CCAUX
DOUT
DONE
CCLK
INITN
DIN
DIN
1
2
3
CC
or V
CCAUX
, whichever is the last to reach its V
t
t
t
SUSCDI
ICFG
SUMCDI
t
SUCFG
3-27
t
SSCL
t
VMC
Valid
MIN
.
t
HCFG
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
t
t
CODO
CODO
t
SSCH
t
t
HSCDI
HMCDI