85104AGILF Integrated Device Technology (Idt), 85104AGILF Datasheet - Page 10

• Manufacturer Part Number: 85104AGILF
• Description: Clock Driver 2-IN HCSL 20-Pin TSSOP Tube
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 85104AGILF

• Package: 20TSSOP
• Configuration: 1 x 2:1
• Input Signal Type: HCSL|LVCMOS|LVDS|LVHSTL|LVPECL|LVTTL|SSTL
• Maximum Output Frequency: 500 MHz
• Operating Supply Voltage: 3.3 V

D
The CLK/nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the V
V
for the HiPerClockS CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples
F
IDT
F
F
CMR
IGURE
IGURE
IFFERENTIAL
IGURE
ICS85104I
LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
™
3.3V
input requirements. Figures 3A to 3E show interface examples
R5,R6 locate near the driver pin.
/ ICS
3.3V
LVPECL
3C. H
3A. H
3E. H
1.8V
™
LVPECL
0.7V HCSL FANOUT BUFFER
R5
100 - 200
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V LVPECL D
IDT H
3.3V LVPECL D
I
I
I
P
P
P
C
ER
ER
ER
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
R6
100 - 200
Zo = 50 Ohm
Zo = 50 Ohm
C
C
C
I
P
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
LOCK
LOCK
ER
C
I
NPUT
S CLK/
S CLK/
LOCK
S CLK/
RIVER
R1
50
S LVHSTL D
3.3V
R3
125
RIVER WITH
C1
C2
I
NTERFACE
R1
84
N
N
N
CLK I
CLK I
CLK I
3.3V
R3
125
R2
50
R4
125
R1
84
R2
84
R4
125
CLK
nCLK
R2
84
NPUT
NPUT
NPUT
AC C
CLK
nCLK
3.3V
3.3V
HiPerClockS
Input
RIVER
HiPerClockS
Input
D
D
D
OUPLE
CLK
nCLK
RIVEN BY
RIVEN BY
RIVEN BY
3.3V
HiPerClockS
Input
PP
and
10
F
only. Please consult with the vendor of the driver component to
confirm the driver termination requirements. For example in Figure
3A, the input termination applies for IDT HiPerClockS LVHSTL
drivers. If you are using an LVHSTL driver from another vendor,
use their termination recommendation.
F
IGURE
IGURE
3.3V
3.3V
3D. H
3B. H
LVDS_Driv er
LVPECL
3.3V LVPECL D
3.3V LVDS D
I
I
P
P
Zo = 50 Ohm
Zo = 50 Ohm
ER
ER
C
C
LOCK
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
ICS85104AGI REV. A FEBRUARY 25, 2009
S CLK/
S CLK/
RIVER
R1
50
RIVER
R3
50
N
N
R2
50
CLK I
CLK I
R1
100
CLK
nCLK
3.3V
NPUT
NPUT
HiPerClockS
Input
CLK
nCLK
D
D
3.3V
RIVEN BY
RIVEN BY
Receiv er