85104AGILF Integrated Device Technology (Idt), 85104AGILF Datasheet - Page 9

• Manufacturer Part Number: 85104AGILF
• Description: Clock Driver 2-IN HCSL 20-Pin TSSOP Tube
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 85104AGILF

• Package: 20TSSOP
• Configuration: 1 x 2:1
• Input Signal Type: HCSL|LVCMOS|LVDS|LVHSTL|LVPECL|LVTTL|SSTL
• Maximum Output Frequency: 500 MHz
• Operating Supply Voltage: 3.3 V

R
I
CLK I
For applications not requiring the use of a clock input, it can be
left floating. Though not required, but for additional protection, a
1k
CLK/nCLK I
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1k
ground.
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
W
IDT
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_BIAS = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
NPUTS
ECOMMENDATIONS FOR
ICS85104I
LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
IRING THE
™
resistor can be tied from the CLK input to ground.
/ ICS
NPUT
:
™
0.7V HCSL FANOUT BUFFER
ONTROL
NPUTS
D
IFFERENTIAL
resistor can be used.
P
INS
U
NUSED
I
NPUT TO
resistor can be tied from CLK to
F
IGURE
I
NPUT AND
A
Single Ended Clock Input
A
PPLICATION
CCEPT
2. S
INGLE
O
S
UTPUT
INGLE
E
C1
0.1u
NDED
V_Bias
DD
E
/2 is
P
NDED
S
INS
I
IGNAL
NFORMATION
9
L
O
D
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
of R1 and R2 might need to be adjusted to position the V_BIAS
in the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
D
EVELS
IFFERENTIAL
R1
1K
R2
1K
UTPUTS
RIVING
V
DD
CLK
nCLK
D
:
IFFERENTIAL
O
UTPUT
s
I
ICS85104AGI REV. A FEBRUARY 25, 2009
NPUT
DD
= 3.3V, V_BIAS should be 1.25V