M34E02-FMC6TG STMicroelectronics, M34E02-FMC6TG Datasheet - Page 14

• Manufacturer Part Number: M34E02-FMC6TG
• Description: UFDFPN 2X3X0.6 8L 0.5MM PITCH
• Manufacturer: STMicroelectronics

Specifications of M34E02-FMC6TG

• Lead Free Status / Rohs Status: Compliant

Device operation
3.7
3.7.1
3.7.2
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Write operations
Following a Start condition the bus master sends a device select code with the RW bit reset
to 0. The device acknowledges this, as shown in
The device responds to the address byte with an acknowledge bit, and then waits for the
data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10
memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the
internal Write cycle.
During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and
the device does not respond to any requests.
Byte Write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is hardware write-protected, the device replies to the data byte with
NoAck, and the location is not modified. If, instead, the addressed location is not Write-
protected, the device replies with Ack. The bus master terminates the transfer by generating
a Stop condition, as shown in
Page Write
The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits are the same. If more bytes are sent than will fit up to the end of the
page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If the addressed location is hardware write-protected,
the device replies to the data byte with NoAck, and the locations are not modified. After each
byte is transferred, the internal byte address counter (the 4 least significant address bits
only) is incremented. The transfer is terminated by the bus master generating a Stop
condition.
th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal
Doc ID 10367 Rev 11
Figure 8
Figure
8, and waits for an address byte.
M34E02, M34E02-F