R1LP0108ESP-5SI#S0 Renesas Electronics America, R1LP0108ESP-5SI#S0 Datasheet - Page 14

• Manufacturer Part Number: R1LP0108ESP-5SI#S0
• Manufacturer: Renesas Electronics America

R1LP0108E Series
Low Vcc Data Retention Characteristics
Note
R10DS0029EJ0200 Rev.2.00
2011.01.14
Chip deselect to data retention time
Operation recovery time
Data retention current
1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer and Din buffer. If CS2 controls data
V
CC
retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state.
If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input
levels (address, WE# ,OE#, DQ) can be in the high impedance state.
for data retention
Parameter
Symbol
I
t
V
CCDR
CDR
t
DR
R
Min.
2.0
0
5
-
-
-
-
Typ.
1
-
-
-
-
-
-
*1
Max.
5.5
10
2
3
8
-
-
Unit
ms
μA
μA
μA
μA
ns
V
Vin ≥ 0V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ Vcc-0.2V,
~+25°C
~+40°C
~+70°C
~+85°C
See retention waveform.
CS2 ≥ Vcc-0.2V
Test conditions
Vcc=3.0V, Vin ≥ 0V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ Vcc-0.2V,
CS2 ≥ Vcc-0.2V
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