LFE3-150EA-8FN1156C Lattice, LFE3-150EA-8FN1156C Datasheet - Page 3

• Manufacturer Part Number: LFE3-150EA-8FN1156C
• Description: IC FPGA 149K LUTS 586I/O FN1156
• Manufacturer: Lattice
• Series: ECP3r

Specifications of LFE3-150EA-8FN1156C

• Number Of Logic Elements/cells: 149000
• Number Of Labs/clbs: 18625
• Total Ram Bits: 7014400
• Number Of I /o: 586
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

High-Value, Low-Power
Serial Protocol Solutions
LatticeECP3 MULTI-PROTOCOL STACK


CPRI LOW LATENCY OPTION



ENHANCED SMPTE SUPPORT


* CPRI Supported By Extension
Supported
PHYs
Soft IP
Embedded
SERDES
and
Physical
Coding
Sub-Layers
(PCS)
RX
Supports commonly used Ethernet protocols (1GbE, SGMII, and XAUI),
Wireless protocols, such as CPRI, are supported by extension
Supports PCI Express and Serial RapidIO
Supports data rates for up to 3.072Gbps CPRI links
Supports multi-hop RRH applications through innovative low-latency
variation SERDES implemementation
Library of CPRI, JESD204A, SRIO, Ethernet and DSP cores and reference
designs for single-chip RF and baseband implementations
Any rate, any channel, any direction for SD/HD and 3G
Truly independent Rx/Tx multi-rate support for SD/HD/3G!
HD
Rec Clk 3
Tx 3
Rx 3
CDR
• New x11 divider setting
• Added independent Rx clocking per channel
Word Aligner Variation
3G
Recovered Clock
Offset Registers
Reported in
Des
3G
Auto Negotiation
GbE / SGMII*
Clock Tolerance
Compensation
State Machine
GbE & SGMII
Synchronize
Rec Clk 2
Rx Link
Rx 2
8b/10b
Tx 2
Tx Rx
SERDES/PCS
Offset
WA
HD
Reference Clock
10b/8b
Bypassable Bridge FIFO
Domain Implementation
148.35 MHz
148.5 MHz
SMPTE Divider Settings
XAUI State Machine
Clock Tolerance
Compensation
for Single Clock
Synchronize
DIV2: 1.485 Gbps
DIV11: 270 Mbps
DIV1: 2.97 Gbps
XAUI PCS
Soft Logic
Alignment
Rx
Channel
Rx Link
8b/10b
XAUI
Tx Rx
PLL (x20)
LatticeECP3 SERDES
Fabric
Bypassable
Bridge
FIFO
Reference Clock
148.5 MHz
Tx
ff_rxi_clk
8b or 16b
Clock Tolerance
Compensation
rx data
To SCI
Synchronize
Soft Logic
Alignment
Express
PCIe PHY
Framing
Channel
LTSSM
Rx Link
8b/10b
Tx Rx
PCI
SD
FPGA Fabric
Rec Clk 1
Rx 1
Tx 1
IP Core
CPRI
3G
Clock Tolerance
State Machine
Compensation
Synchronize
User Interface
Fractional
RapidIO
Soft Logic
Alignment
RX State
Machine
Channel
Rx Link
Serial
8b/10b
Tx Rx
IP Core
HD
Rec Clk 0
Rx 0
Tx 0
rx_clk
SD
Evaluation &
Development
Boards
To accelerate your design development,
Lattice offers several development boards
to support LatticeECP3 designs. These
boards enable you to evaluate the benefits
and capabilities of LatticeECP3 devices in
a lab setting.
The LatticeECP3 Versa Evaluation Board is the
industry's lowest cost FPGA board with PCI Ex-
press and two Gigabit Ethernet ports. It is use-
ful for appreciating the quality of LatticeECP3
SERDES and developing a wide-range of net-
working and system design applications.
The Lattice HDR-60 Video Camera Develop-
ment Kit is an FPGA-based HDR camera capa-
ble of supporting 1080p60 over HDMI/DVI out-
put. The design needs no external frame buffer,
enabling the lowest cost FPGA HDR camera
BOM. Features include Auto White Balance,
industry's fastest auto-exposure, extremely low-
latency and 120dB High Dynamic Range.
The LatticeECP3 Serial Protocol Board provides
a platform to evaluate the LatticeECP3 device's
multi-protocol serial protocol functionality as
well as DDR2 and DDR3 memory interfaces.
The LatticeECP3 Video Protocol Board provides
a platform to evaluate the LatticeECP3 device's
multi-rate 3G/HD/SDI and 7:1 LVDS capabilities.
Breakout options for other display interfaces are
also available.