MT46H8M32LFB5-6IT:H Micron Technology Inc, MT46H8M32LFB5-6IT:H Datasheet - Page 43

• Manufacturer Part Number: MT46H8M32LFB5-6IT:H
• Description: MICMT46H8M32LFB5-6_IT:H MDDDR
• Manufacturer: Micron Technology Inc

PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
4. AUTO REFRESH and LOAD MODE REGISTER commands can only be issued when all
5. All states and sequences not shown are illegal or reserved.
6. Requires appropriate DM masking.
7. A WRITE command can be applied after the completion of the READ burst; otherwise, a
executed with auto precharge disabled and then followed with the earliest possible
PRECHARGE command that still accesses all of the data in the burst. For write with auto
precharge, the precharge period begins when
precharge was disabled. The access period starts with registration of the command and
ends when the precharge period (or
precharge such that when a read with auto precharge is enabled or a write with auto
precharge is enabled, any command to other banks is supported, as long as that com-
mand does not interrupt the read or write data transfer already in process. In either
case, all other related limitations apply (i.e., contention between read data and write
data must be avoided).
3b. The minimum delay from a READ or WRITE command (with auto precharge enabled)
to a command to a different bank is summarized below.
banks are idle.
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
From
Command
WRITE with
Auto Precharge
READ with
Auto Precharge
To Command
READ or READ with auto precharge
WRITE or WRITE with auto pre-
charge
PRECHARGE
ACTIVE
READ or READ with auto precharge
WRITE or WRITE with auto pre-
charge
PRECHARGE
ACTIVE
43
256Mb: x16, x32 Mobile LPDDR SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RP) begins. This device supports concurrent auto
t
WR ends, with
(with Concurrent Auto
© 2008 Micron Technology, Inc. All rights reserved.
[1 + (BL/2)]
t
WR measured as if auto
Minimum Delay
[CL + (BL/2)]
Precharge)
(BL/2) ×
(BL/2)
1
1
1
1
Truth Tables
t
t
t
t
CK
CK
CK
CK
t
CK +
t
CK
t
CK
t
CK
t
WTR