MT9075BP1 Zarlink, MT9075BP1 Datasheet - Page 21

• Manufacturer Part Number: MT9075BP1
• Description: PB FREE E1 SINGLE CHIP TRANSCEIVER
• Manufacturer: Zarlink

of the device on pin RxDL (pin 40 in PLCC, pin 21 in MQFP). In order to facilitate the attachment of this data
stream to a Data Link controller, the clock signal RxDLCLK consists of positive pulses, of nominal width of 244
ns, during the S
address 10H of master control page 01H. No DL data will be lost or repeated when a receive frame slip occurs.
See Figures 13-16 for timing requirements.
Timeslot 16
Channel 16 may be used to create a transparent 64 kb/s clear channel. In this event CSTi (pin 6 in PLCC, pin 71 in
MQFP) becomes the data input pin for channel 16 transmit data, and CSTo (pin 5 in PLCC, pin 70 in MQFP)
becomes a 64 kb/s serial output link. The CSTo output link is synchronous to the extracted clock timebase. The pin
Rx64KCK (pin 47 in PLCC, pin 35 in MQFP) provides a 64 kHz clock for use with 64 kb/s data emanating from
CSTo. The 64 kb/s input data from CSTi is clocked in with an internal 64 kHz clock synchronous to the I/O pin C4b
(pin 45 in PLCC, pin 33 in MQFP) timebase. The internal clock toggles coincident with every second ST-BUS
channel boundary, with the first rising edge of a frame occurring at the beginning of ST-BUS channel 2.
Dual HDLC
The MT9075B has two identical HDLC controllers (HDLC0, HDLC1) for the S
The following features are common to both HDLC controllers:
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HDLC0 Functions
When connected to the Data Link (DL) HDLC0 will operate at a selected bit rate of 4, 8, 12, 16 or 20 kbits/sec.
HDLC0 can be selected by setting the control bit HDLC0 (bit 7) to one in page 01H, address 14H. When this bit is
zero all interrupts from HDLC0 are masked. For more information refer to following sections.
HDLC1 Functions
This controller may be connected to time slot 16 under Common Channel Signalling (CCS) mode. It should be
noted that the AIS16S function (page 03H, address 19H) will always be active and the TAIS16 function (page 01H,
address 16H) will override all other transmit signalling.
HDLC1 can be selected by setting the control bit HDLC1 (bit 6) to one in page 01H, address 14H. When this bit is
zero all interrupts from HDLC1 are masked.
HDLC Overview
The HDLC handles the bit oriented packetized data transmission as per X.25 level two protocol defined by CCITT. It
provides flag and abort sequence generation and detection, zero insertion and deletion, and Frame Check
Sequence (FCS) generation and detection. A single byte, dual byte and all call address in the received frame can
be recognized. Access to the receive FCS and inhibiting of transmit FCS for terminal adaptation are also provided.
Each HDLC controller has a 128 byte deep FIFO associated with it. The status and interrupt flags are
programmable for FIFO depths that can vary from 16 to 128 bytes in steps of 16 bytes. These and other features
are enabled through the HDLC control registers on page 0BH and 0CH.
Independent transmit and receive FIFO's;
Receive FIFO maskable interrupts for nearly full (programmable interrupt levels) and overflow conditions;
Transmit FIFO maskable interrupts for nearly empty (programmable interrupt levels) and underflow
conditions;
Maskable interrupts for transmit end-of-packet and receive end-of-packet;
Maskable interrupts for receive bad-frame (includes frame abort);
Transmit end-of-packet and frame-abort functions.
a
bit cell times that are selected for the data link. Again, this selection is made by programming
Zarlink Semiconductor Inc.
MT9075B
21
a
bits and channel 16 respectively.
Data Sheet