MT9075BP1 Zarlink, MT9075BP1 Datasheet - Page 44

• Manufacturer Part Number: MT9075BP1
• Description: PB FREE E1 SINGLE CHIP TRANSCEIVER
• Manufacturer: Zarlink

Bit
7
6
5
4
3
2
1
0
Table 21 - Interrupt, Signalling and BERT Control Word (Page 01H, Address 1AH
CNTCLR
64KCCS
TxCCS
RPSIG
Name
SPND
INTA
MSN
ODE
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Output Data Enable. If one, the DSTo and CSTo output drivers
function normally. When low, DSTo and CSTo will be tristated.
Note: When ODE =1, DSTo and CSTo can be individually tristated by
DSToDE and CSToDE (page 01H, address 16H) respectively.
Suspend Interrupts. If one, the IRQ output (pin 12 in PLCC, 85 in
MQFP) will be in a high-impedance state and all interrupts will be
ignored. If zero, the IRQ output will function normally.
Interrupt Acknowledge. A zero-to-one or one-to-zero transition will
clear any pending interrupt and make IRQ high.
Transmit Common Channel Signalling. If one, the transmit section of
the device is in common channel signalling (CCS) mode. If zero, it is in
Channel Associated Signalling (CAS) mode.
Register Programmed Signalling. If one, the transmit CAS signalling
will be controlled by programming page 05H. If zero, the transmit CAS
signalling will be controlled through the CSTi stream.
Counter Clear. If one, all status counters are cleared and held low.
Zero for normal operation.
Most Significant Signalling Nibble. If one, the CSTo and CSTi
channel associated signalling nibbles will be valid in the most
significant portion of each ST-BUS time slot. If zero, the CSTo and
CSTi channel associated signalling nibbles will be valid in the least
significant portion of each ST-BUS time slot.
64 Kbits/s Common Channel Signalling. If one, common channel
signalling information is sourced from CSTi, and common channel
signalling information is clocked out of CSTo. The transmit clock is an
internal clock. This 64 KHz clock is divided down from C4b and is
synchronous with the STBUS channel boundaries. The rising edges of
the clock occur between channels 1 and 2; 5 and 6; 9 and 10; 13 and
14; 17 and 18; 21 and 22; 25 and 26; 29 and 30. The receive clock is
synchronous with the same channel times, but derived from the
extracted clock timebase. The CCS receive clock is driven out on
Rx64KCK (pin 47 in PLCC, 35 in MQFP) when this bit is set. If zero
CSTi and CSTo have 2.048 mb/s bit rates and operate as per Tables
66 to 71.
Zarlink Semiconductor Inc.
MT9075B
44
Functional Description
Data Sheet