AD5380BST-5 Analog Devices Inc, AD5380BST-5 Datasheet - Page 10

• Manufacturer Part Number: AD5380BST-5
• Description: IC DAC 14BIT 12C 40CH 5V 100LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5380BST-5

• Design Resources: 40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5380 (CN0007) Output Channel Monitoring Using AD5380 (CN0008)
• Settling Time: 6µs
• Number Of Bits: 14
• Data Interface: I²C, Parallel, Serial
• Number Of Converters: 40
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 125mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• For Use With: EVAL-AD5380EB - BOARD EVAL FOR AD5380
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD5380
I
DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T
unless otherwise noted.
Table 7.
Parameter
F
t
t
t
t
t
t
t
t
t
t
t
C
1
2
3
4
1
2
3
4
5
6
7
8
9
10
11
2
Guaranteed by design and characterization, not production tested.
See Figure 6.
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.
SCL
b
3
C SERIAL INTERFACE
SDA
SCL
1, 2
t
9
CONDITION
Limit at T
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
300
0
300
20 + 0.1C
400
START
t
4
b
MIN
t
4
3
, T
MAX
t
10
t
6
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Figure 6. I
2
C Compatible Serial Interface Timing Diagram
t
2
Description
SCL cycle time
t
t
t
t
t
t
t
t
t
Capacitive load for each bus line
SCL clock frequency
t
t
t
t
t
t
HIGH
LOW
HD,STA
SU,DAT
HD,DAT
HD,DAT
SU,STA
SU,STO
BUF
R
R
F
F
F
F
Rev. A | Page 10 of 40
, rise time of SCL and SDA when receiving
, rise time of SCL and SDA when receiving (CMOS compatible)
, fall time of SDA when transmitting
, fall time of SDA when receiving (CMOS compatible)
, fall time of SCL and SDA when receiving
, fall time of SCL and SDA when transmitting
, bus free time between a STOP and a START condition
, SCL low time
, SCL high time
, setup time for repeated start
, data setup time
, stop condition setup time
, start/repeated start condition hold time
, data hold time
, data hold time
t
11
t
5
CONDITION
REPEATED
START
t
7
t
4
t
1
MIN
to T
MAX
,
CONDITION
STOP
t
8