AD5380BST-5 Analog Devices Inc, AD5380BST-5 Datasheet - Page 11

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AD5380BST-5

Manufacturer Part Number
AD5380BST-5
Description
IC DAC 14BIT 12C 40CH 5V 100LQFP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD5380BST-5

Design Resources
40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5380 (CN0007) Output Channel Monitoring Using AD5380 (CN0008)
Settling Time
6µs
Number Of Bits
14
Data Interface
I²C, Parallel, Serial
Number Of Converters
40
Voltage Supply Source
Single Supply
Power Dissipation (max)
125mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
For Use With
EVAL-AD5380EB - BOARD EVAL FOR AD5380
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
PARALLEL INTERFACE
DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T
unless otherwise noted.
Table 8.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Guaranteed by design and characterization, not production tested.
All input signals are specified with t
See Figure 7.
See Figure 29.
4
4
1,2, 3
Limit at T
4.5
4.5
20
20
0
0
4.5
4.5
20
700
30
670
30
20
100
20
0
100
8
20
35
R
= t
R
MIN
= 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
, T
MAX
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
ns min
μs typ
ns min
μsmax
Rev. A | Page 11 of 40
Description
REG0, REG1, address to WR rising edge setup time
REG0, REG1, address to WR rising edge hold time
CS pulse width low
WR pulse width low
CS to WR falling edge setup time
WR to CS rising edge hold time
Data to WR rising edge setup time
Data to WR rising edge hold time
WR pulse width high
Minimum WR cycle time (single-channel write)
WR rising edge to BUSY falling edge
BUSY pulse width low (single-channel update)
WR rising edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
LDAC rising edge to WR rising edge
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
MIN
to T
MAX
,
AD5380

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