AD5382BST-5 Analog Devices Inc, AD5382BST-5 Datasheet - Page 31

• Manufacturer Part Number: AD5382BST-5
• Description: IC DAC 14BIT 32CH 5V 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5382BST-5

• Design Resources: 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5382 (CN0011) AD5382 Channel Monitor Function (CN0012)
• Settling Time: 8µs
• Number Of Bits: 14
• Data Interface: Serial, Parallel
• Number Of Converters: 32
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 65mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• For Use With: EVAL-AD5382EB - BOARD EVAL FOR AD5382
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MICROPROCESSOR INTERFACING
Parallel Interface
The AD5382 can be interfaced to a variety of 16-bit microcon-
trollers or DSP processors. Figure 35 shows the AD5382 family
interfaced to a generic 16-bit microcontroller/DSP processor.
The lower address lines from the processor are connected to
A0–A4 on the AD5382. The upper address lines are decoded
to provide a CS , LDAC signal for the AD5382. The fast interface
timing of the AD5382 allows direct interface to a wide variety
of microcontrollers and DSPs, as shown in
AD5382 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR = 1), Clock Polarity bit
(CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the
SCLK of the AD5382, the MOSI output drives the serial data
line (DIN) of the AD5382, and the MISO input is driven from
DOUT. The SYNC signal is derived from a port line (PC7).
1
ADDITIONAL PINS OMITTED FOR CLARITY.
DSP PROCESSOR
μCONTROLLER/
UPPER BITS OF
ADDRESS BUS
DATA
BUS
Figure 35
R/W
D15
D0
A4
A3
A2
A1
A0
1
.
Figure 35. AD5382-to-Parallel Interface
Rev. B | Page 31 of 40
ADDRESS
DECODE
When data is being transmitted to the AD5382, the SYNC line
is taken low (PC7). Data appearing on the MOSI output is valid
on the falling edge of SCK. Serial data from the 68HC11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
MC68HC11
REG1
REG0
D13
D0
CS
LDAC
A4
A3
A2
A1
A0
WR
MISO
MOSI
1
SCK
PC7
Figure 34. AD5382-to-MC68HC11 Interface
AD5382
1
DVDD
SER/PAR
RESET
SDO
DIN
SCLK
SYNC
SPI/I
AD5382
2
C
AD5382
1