AD5453YUJ-REEL7 Analog Devices Inc, AD5453YUJ-REEL7 Datasheet - Page 23

• Manufacturer Part Number: AD5453YUJ-REEL7
• Description: IC DAC 14BIT MULT TSOT23-8
• Manufacturer: Analog Devices Inc

Specifications of AD5453YUJ-REEL7

• Design Resources: Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055)
• Settling Time: 180ns
• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 55µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: TSOT-23-8, TSOT-8
• For Use With: EVAL-AD5453EB - BOARD EVAL FOR AD5453
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The SYNC signal is derived from a port line (PC7). When data
is being transmitted to the AD5450/AD5451/AD5452/AD5453,
the SYNC line is taken low (PC7). Data appearing on the MOSI
output is valid upon the falling edge of SCK. Serial data from
the 68HC11 is transmitted in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Data is transmitted
MSB first. To load data to the DAC, PC7 is left low after the first
eight bits are transferred, and a second serial write operation is
performed to the DAC. PC7 is taken high at the end of this
procedure.
If the user wants to verify the data previously written to the
input shift register, the SDO line can be connected to MISO of
the MC68HC11. In this configuration with SYNC low, the shift
register clocks data out upon the rising edges of SCLK.
MICROWIRE-to-
AD5450/AD5451/AD5452/AD5453 Interface
Figure 59 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out
upon the falling edge of the serial clock, SK, and is clocked into
the DAC input shift register upon the rising edge of SK, which
corresponds to the falling edge of the DAC’s SCLK.
PIC16C6x/PIC16C7x-to-
AD5450/AD5451/AD5452/AD5453 Interface
The PIC16C6x/PIC16C7x synchronous serial port (SSP) is
configured as an SPI master with the clock polarity bit (CKP) = 0.
This is done by writing to the synchronous serial port control
register (SSPCON); see the PIC16/PIC17 Microcontroller User
Manual .
In this example, I/O Port RA1 is used to provide a SYNC signal
and enable the serial port of the DAC. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, two consecutive write operations are
required. Figure 60 shows the connection diagram.
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
MICROWIRE*
MC68HC11*
Figure 59. MICROWIRE-to-AD5450/AD5451/AD5452/AD5453 Interface
Figure 58. MC68HC11-to-AD5450/AD5451/AD5452/AD5453 Interface
MOSI
SCK
PC7
SO
SK
CS
SYNC
SDIN
AD5452/AD5453*
SCLK
AD5450/AD5451/
SCLK
SDIN
SYNC
AD5452/AD5453*
AD5450/AD5451/
Rev. B | Page 23 of 28
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which a
AD5450/AD5451/AD5452/AD5453 DAC is mounted should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. If the DAC is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device.
These DACs should have ample supply bypassing of 10 μF in
parallel with 0.1 μF on the supply located as close to the package
as possible, ideally right up against the device. The 0.1 μF
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), like the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1 μF to 10 μF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Components, such as clocks, that produce fast switching signals
should be shielded with a digital ground to avoid radiating noise
to other parts of the board, and they should never be run near
the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is the best solution, but its use is not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane and signal
traces are placed on the solder side.
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between V
matched to minimize gain error. To optimize high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
*ADDITIONAL PINS OMITTED FOR CLARITY
PIC16C6x/PIC16C7x*
Figure 60. PIC16C6x/7x-to-AD5450/AD5451/AD5452/AD5453 Interface
SCK/RC3
AD5450/AD5451/AD5452/AD5453
SDI/RC4
RA1
REF
and R
FB
AD5452/AD5453*
AD5450/AD5451/
SCLK
SDIN
SYNC
should also be