AD5453YUJ-REEL7 Analog Devices Inc, AD5453YUJ-REEL7 Datasheet - Page 7

• Manufacturer Part Number: AD5453YUJ-REEL7
• Description: IC DAC 14BIT MULT TSOT23-8
• Manufacturer: Analog Devices Inc

Specifications of AD5453YUJ-REEL7

• Design Resources: Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055)
• Settling Time: 180ns
• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 55µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: TSOT-23-8, TSOT-8
• For Use With: EVAL-AD5453EB - BOARD EVAL FOR AD5453
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
TSOT
1
2
3
4
5
6
7
8
Pin No.
MSOP
8
7
6
5
4
3
2
1
SYNC
Mnemonic
R
V
V
SYNC
SDIN
SCLK
GND
I
V
OUT
Figure 3. TSOT Pin Configuration
R
V
FB
REF
DD
REF
FB
DD
1
1
2
3
4
AD5450/
AD5451/
AD5452/
AD5453
Description
DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external amplifier output.
DAC Reference Voltage Input.
Positive Power Supply Input. These parts can operate from a supply of 2.5 V to 5.5 V.
Active Low Control Input. This is the frame synchronization signal for the input data. Data is loaded to the
shift register upon the active edge of the following clocks.
Serial Data Input. Data is clocked into the 16-bit input register upon the active edge of the serial clock
input. By default, in power-up mode data is clocked into the shift register upon the falling edge of SCLK.
The control bits allow the user to change the active edge to a rising edge.
Serial Clock Input. By default, data is clocked into the input shift register upon the falling edge of the serial
clock input. Alternatively, by means of the serial control bits, the device can be configured such that data is
clocked into the shift register upon the rising edge of SCLK.
Ground Pin.
DAC Current Output.
8
7
6
5
I
GND
SCLK
SDIN
OUT
1
Rev. B | Page 7 of 28
AD5450/AD5451/AD5452/AD5453
SCLK
I
SDIN
OUT
GND
Figure 4. MSOP Pin Configuration
1
1
2
3
4
AD5452/
AD5453
8
7
6
5
R
V
V
SYNC
REF
DD
FB