HI1178JCQ Intersil, HI1178JCQ Datasheet - Page 10

• Manufacturer Part Number: HI1178JCQ
• Description: CONV D/A 8BIT TRPL 40MHZ 48-PQFP
• Manufacturer: Intersil

Specifications of HI1178JCQ

• Number Of Bits: 8
• Data Interface: Parallel
• Number Of Converters: 3
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 240mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-MQFP, 48-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -

Application Circuit
Notes On Operation
• How to select the output resistance
• Phase Relation Between Data and Clock
The HI1178 is a current-output D/A converter. To obtain
the output voltage, connect the resistance to IO pin (RO,
GO, BO). For specifications we have:
Calculate the output resistance value from the relation of
V
resistance is connected to reference current pin I
some cases, however, this turns out to be a value that
does not actually exist. In such a case a value close to it
can be used as a substitute. Here please note that V
becomes V
nected to IO while R' is connected to I
resistance value can curb power consumption. On the
other hand glitch energy and data settling time will
inversely increase. Set the most suitable value according
to the desired application.
Output Full Scale Voltage
Output Full Scale Current
FS
= I
FS
FS
X R. Also, 16 times resistance of the output
= V
R(RED)IN
G(GREEN)IN
REF
X 16R/R'. R is the resistance con-
(MSB)
10
(LSB)
(LSB)
V
I
FS
10
11
12
FS
1
2
3
4
5
6
7
8
9
DV
= less than 15 [mA]
48
= less than 2.0 [V]
13 14 15 16
DD
REF
47
AV
46
. Increasing the
DD
45
44
17
REF
43
18
HI1178
0.1µ
. In
FS
42
19
FIGURE 11.
HI1178
B(BLUE)IN
41
20
40
21
39
22
• V
38
23
To obtain the expected performance as a D/A converter, it
is necessary to set properly the phase relation between
data and clock applied from the exterior. Be sure to satisfy
the provisions of the set up time (t
stipulated in the Electrical Characteristics.
To reduce noise effects separate analog and digital
systems in the device periphery. For V
and analog, bypass respective GNDs by using a ceramic
capacitor of 0.1µF, as close as possible to the pin.
(GCK)
(RCK)
(BCK)
DD
37
24
, V
36
35
34
33
32
31
30
29
28
27
26
25
SS
2V
DV
200
AV
200
200
SS
0.1µ
SS
DV
SS
AV
AV
CLOCK IN
1K
AV
AV
SS
SS
B(BLUE)OUT
DD
SS
G(GREEN)OUT
R(RED)OUT
3.3K
AV
SS
S
) and hold time (t
DD
pins, both digital
H
) as