HI3-DAC80V-5 Intersil, HI3-DAC80V-5 Datasheet - Page 5

• Manufacturer Part Number: HI3-DAC80V-5
• Description: CONV D/A 12BIT OUTPUT AMP 24PDIP
• Manufacturer: Intersil

Specifications of HI3-DAC80V-5

• Settling Time: 1.5µs
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 75°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power Dissipation (max): -

Definitions of Specifications
Digital Inputs
The Hl-DAC80V accepts digital input codes in
complementary binary, complementary offset binary, and
complementary two’s complement binary.
Settling Time
That interval between application of a digital step input, and
final entry of the analog output within a specified window
about the settled value. Intersil Corporation usually specifies
a unipolar 10V full scale step, to be measured from 50% of
the input digital transition, and a window of
the final value. The device output is then rated according to
the worst (longest settling) case: low to high, or high to low.
In a 12-bit system
Thermal Drift
Thermal drift is based on measurements at 25
(T
for the high (T
larger of the two values is given as a specification
representing worst case drift.
Gain Drift, Offset Drift, Reference Drift and Total Bipolar Drift
are calculated in parts per million per
NOTE: FSR = Full Scale Output Voltage - Zero Scale Output
Voltage.
or FSR (25
V
GainDrift
OffsetDrift
ReferenceDrift
TotalBipolarDrift
†
MSB...LSB
FSR = FSR (T
O
000...000
100...000
111...111
011...111
DIGITAL
H
Invert MSB with external inverter to obtain CTC Coding.
INPUT
) and low (T
= Steady State response to any input code.
=
=
o
------------------------------- -
C) - FSR (T
Mid Scale-1 LSB
-------------------------------------
FSR
+
H
Offset
1
=
+ Full Scale
STRAIGHT
MENTARY
FSR
L
COMPLE-
H
/
-25
BINARY
2
) temperatures. Drift calculations are made
---------------------------------------
) - FSR (25
FSR
=
Full Scale
Zero
V
o
1
------------------------------- -
REF
C) and low (25
/
V
V
2
C
O
REF
FSR
LSB = 0.012% of FSR.
L
C
).
10
TABLE 1.
ANALOG OUTPUT
6
10
C
C
o
C),
5
6
+ Full Scale
- Full Scale
MENTARY
COMPLE-
OFFSET
BINARY
-1 LSB
10
10
Zero
6
6
o
C-T
o
C as follows:
L
) ranges, and the
COMPLEMENT
1
/
2
o
+ Full Scale
- Full Scale
MENTARY
COMPLE-
C, at high
LSB about
TWO’S
-LSB
Zero
HI-DAC80V
†
Total Bipolar Drift (TBD) is the variation of output voltage
with temperature, in the bipolar mode of operation. It
represents the net effect of drift in Gain, Offset, Linearity and
Reference Voltage. Total Bipolar Drift values are calculated,
based on measurements as explained above. Gain and
Offset need not be calibrated to zero at 25
limits for TBD apply for any input code and for any power
supply setting within the specified operating range.
Accuracy
Linearity Error (Short for “Integral Linearity Error.” Also,
sometimes called “Integral Nonlinearity” and “Nonlinearity”.)
The maximum deviation of the actual transfer characteristic
from an ideal straight line. The ideal line is positioned
according to end-point linearity for D/A converter products
from Intersil Corporation, i.e., the line is drawn between the
end-points of the actual transfer characteristic (codes 00...0
and 11...1).
Differential Linearity Error The difference between one
LSB and the output voltage change corresponding to any
two consecutive codes. A Differential Nonlinearity of 1 LSB
or less guarantees monotonicity.
Monotonicity The property of a D/A converter’s transfer
function which guarantees that the output derivative will not
change sign in response to a sequence of increasing (or
decreasing) input codes. That is, the only output response to
a code change is to remain constant, increase for Increasing
code, or decrease for decreasing code.
Total Error The net output error resulting from all internal
effects (primarily non-ideal Gain, Offset, Linearity and
Reference Voltage). Supply voltages may be set to any
values within the specified operating range. Gain and offset
errors must be calibrated to zero at 25
limits for Total Error apply for any input code and for any
temperature within the specified operating range.
Power Supply Sensitivity
Power Supply Sensitivity is a measure of the change in gain
and offset of the D/A converter resulting from a change in
-V
expressed as full scale range percent of change divided by
power supply percent change.
Glitch
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times.
Worst case glitches usually occur at half-scale, i.e., the
major carry code transition from 011...1 to 100...0 or vice
versa. For example, if turn ON is greater than OFF for
011...1 to 100...0, an intermediate state of 000...0 exists,
such that, the output momentarily glitches toward zero
PSS
S
, or +V
=
------------------------------------------------------------------ -
------------------------------------------------------------------ -
FullScaleRange 100
S
FSR Nominal
supplies. It is specified under DC conditions and
--------------------------------- -
V
S
V
(Nominal)
S
100
o
C. Then the specified
o
C. The specified