EPM1270F256C4 Altera, EPM1270F256C4 Datasheet - Page 24
![IC MAX II CPLD 1270 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM1270F256C4
Manufacturer Part Number
EPM1270F256C4
Description
IC MAX II CPLD 1270 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM1270F256C4
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
212
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-1140
EPM1270F256C4ES
EPM1270F256C4ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM1270F256C4
Manufacturer:
ALTBRA
Quantity:
1 572
Company:
Part Number:
EPM1270F256C4N
Manufacturer:
ALTERA
Quantity:
672
Part Number:
EPM1270F256C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
2–16
Table 2–2. MAX II Device Routing Scheme
Global Signals
MAX II Device Handbook
LUT Chain
Register Chain
Local
Interconnect
DirectLink
Interconnect
R4 Interconnect
C4 Interconnect
LE
UFM Block
Column IOE
Row IOE
Note to
(1) These categories are interconnects.
Source
Table
2–2:
Chain
LUT
v
—
—
—
—
—
—
—
—
—
The UFM block communicates with the logic array similar to LAB-to-LAB interfaces.
The UFM block connects to row and column interconnects and has local interconnect
regions driven by row and column interconnects. This block also has DirectLink
interconnects for fast connections to and from a neighboring LAB. For more
information about the UFM interface to the logic array, see
Block” on page
Table 2–2
Each MAX II device has four dual-purpose dedicated clock pins (GCLK[3..0], two
pins on the left side and two pins on the right side) that drive the global clock network
for clocking, as shown in
purpose I/O if they are not used to drive the global clock network.
The four global clock lines in the global clock network drive throughout the entire
device. The global clock network can provide clocks for all resources within the
device including LEs, LAB local interconnect, IOEs, and the UFM block. The global
clock lines can also be used for global control signals, such as clock enables,
synchronous or asynchronous clears, presets, output enables, or protocol control
signals such as TRDY and IRDY for PCI. Internal logic can drive the global clock
network for internally-generated global clocks and control signals.
the various sources that drive the global clock network.
Register
Chain
v
—
—
—
—
—
—
—
—
—
shows the MAX II device routing scheme.
Local
2–18.
(1)
—
—
v
v
v
v
v
—
—
—
DirectLink
Figure
(1)
v
v
v
—
—
—
—
—
—
—
2–13. These four pins can also be used as general-
R4
—
—
—
—
v
v
v
v
—
v
(1)
Destination
C4
v
v
v
v
v
v
—
—
—
—
(1)
v
v
v
—
—
—
—
—
—
—
LE
“User Flash Memory
Block
© October 2008 Altera Corporation
UFM
v
—
—
—
—
—
—
—
—
—
Chapter 2: MAX II Architecture
Figure 2–13
Column
IOE
v
v
—
—
—
—
—
—
—
—
Global Signals
Row
IOE
v
—
—
v
—
—
—
—
—
—
shows
Fast I/O
(1)
—
—
—
—
—
—
v
—
—
—