XC2C384-10FTG256C Xilinx Inc, XC2C384-10FTG256C Datasheet - Page 2

• Manufacturer Part Number: XC2C384-10FTG256C
• Description: IC CR-II CPLD 384MCELL 256-FBGA
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C384-10FTG256C

• Operating Temperature: 0°C ~ 70°C
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 9.2ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 24
• Number Of Macrocells: 384
• Number Of Gates: 9000
• Number Of I /o: 212
• Mounting Type: Surface Mount
• Package / Case: 256-FTBGA
• Features: JTAG
• Voltage: 1.8V
• Memory Type: CMOS
• No. Of Macrocells: 384
• No. Of I/o's: 212
• Propagation Delay: 7.1ns
• Global Clock Setup Time: 2.9ns
• Frequency: 217MHz
• Supply Voltage Range: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1405

XC2C384 CoolRunner-II CPLD
By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O bank-
ing. Four I/O banks are available on the CoolRunner-II 384
macrocell device that permit easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
The CoolRunner-II 384 macrocell CPLD is I/O compatible
with various I/O standards (see
1.5V I/O compatible with the use of Schmitt-trigger inputs.
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
RealDigital a design technique that makes use of CMOS
technology in both the fabrication and design methodology.
RealDigital design technology employs a cascade of CMOS
gates to implement sum of products instead of traditional
sense amplifier methodology. Due to this technology, Xilinx
CoolRunner-II CPLDs achieve both high-performance and
low power operation.
Supported I/O Standards
The CoolRunner-II 384 macrocell features LVCMOS,
LVTTL, SSTL and HSTL I/O implementations. See
Table 2: I
2
Notes:
1.
Typical I
16-bit up/down, Resetable binary counter (one counter per function block).
CC
CC
(mA)
vs Frequency (LVCMOS 1.8V T
150
100
200
50
0
0
Table
0.023
0
25
1). This device is also
17.5
25
50
A
Figure 1: I
= 25°C)
Table 1
35.03
www.xilinx.com
50
75
(1)
CC
vs Frequency
100
52.53
Frequency (MHz)
for I/O standard voltages. The LVTTL I/O standard is a gen-
eral purpose EIA/JEDEC standard for 3.3V applications that
use an LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
Both HSTL and SSTL I/O standards make use of a V
for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V
I/O compatible with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C384
(1)For information on assigning Vref pins, see XAPP399.
(2) LVCMOS15 requires Schmitt-trigger inputs.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
HSTL_1
SSTL2_1
SSTL3_1
IOSTANDARD
75
Attribute
Frequency (MHz)
125
70.03
100
(2)
150
Output
V
87.53
125
3.3
3.3
2.5
1.8
1.5
1.5
2.5
3.3
CCIO
DS095_01_030705
175
V
Input
105.03
3.3
3.3
2.5
1.8
1.5
1.5
2.5
3.3
CCIO
150
DS095 (v3.2) March 8, 2007
200
Input
V
0.75
1.25
Product Specification
N/A
N/A
N/A
N/A
N/A
(1)
1.5
REF
122.35
175
Termination
Voltage V
Board
0.75
1.25
N/A
N/A
N/A
N/A
N/A
1.5
140.03
200
REF
TT
pin
R