EPM3032ATC44-7 Altera, EPM3032ATC44-7 Datasheet - Page 37
![IC MAX 3000A CPLD 32 44-TQFP](/photos/6/70/67053/544-44-tqfp_sml.jpg)
EPM3032ATC44-7
Manufacturer Part Number
EPM3032ATC44-7
Description
IC MAX 3000A CPLD 32 44-TQFP
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet
1.EPM3032ATC44-10N.pdf
(46 pages)
Specifications of EPM3032ATC44-7
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
2
Number Of Macrocells
32
Number Of Gates
600
Number Of I /o
34
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
2
Family Name
MAX 3000A
# Macrocells
32
Number Of Usable Gates
600
Frequency (max)
166.67MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
2
# I/os (max)
34
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1153
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM3032ATC44-7
Manufacturer:
ALTERA
Quantity:
30
Part Number:
EPM3032ATC44-7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPM3032ATC44-7N/I44-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
t
t
t
t
t
t
f
t
f
t
t
t
t
t
t
t
t
t
t
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
AH
ACO1
ACH
ACL
CPPW
CNT
CNT
ACNT
ACNT
Table 24. EPM3512A External Timing Parameters
Table 25. EPM3512A Internal Timing Parameters (Part 1 of 2)
Symbol
Symbol
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for clear
and preset
Minimum global clock period
Maximum internal global clock
frequency
Minimum array clock period
Maximum internal array clock
frequency
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay,
slow slew rate = off
V
Output buffer and pad delay,
slow slew rate = off
V
CCIO
CCIO
= 3.3 V
= 2.5 V
Parameter
Parameter
(2)
C1 = 35 pF
(3)
(2)
(2),
(2)
(2),
C1 = 35 pF
C1 = 35 pF
Conditions
Conditions
MAX 3000A Programmable Logic Device Family Data Sheet
(4)
(4)
Note (1)
(2)
116.3
116.3
Min
Min
3.0
3.0
0.2
1.0
3.0
-7
-7
Note (1)
Max
Max
Speed Grade
7.8
8.6
8.6
Speed Grade
0.7
0.7
3.1
2.7
0.4
2.2
1.0
0.0
1.0
1.5
87.0
87.0
Min
Min
0.3
1.0
4.0
4.0
4.0
-10
-10
Max
10.4
11.5
11.5
Max
0.9
0.9
3.6
3.5
0.5
2.8
1.3
0.0
1.5
2.0
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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