EPM3064ATC100-10N Altera, EPM3064ATC100-10N Datasheet - Page 3
![IC MAX 3000A CPLD 64 100-TQFP](/photos/6/70/67055/544-100-tqfp_sml.jpg)
EPM3064ATC100-10N
Manufacturer Part Number
EPM3064ATC100-10N
Description
IC MAX 3000A CPLD 64 100-TQFP
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet
1.EPM3032ATC44-10N.pdf
(46 pages)
Specifications of EPM3064ATC100-10N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
66
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-1974
EPM3064ATC100-10N
EPM3064ATC100-10N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM3064ATC100-10N
Manufacturer:
ALTERA
Quantity:
9 500
Company:
Part Number:
EPM3064ATC100-10N
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Altera Corporation
The MAX 3000A architecture supports 100% transistor-to-transistor logic
(TTL) emulation and high–density small-scale integration (SSI),
medium-scale integration (MSI), and large-scale integration (LSI) logic
functions. The MAX 3000A architecture easily integrates multiple devices
ranging from PALs, GALs, and 22V10s to MACH and pLSI devices.
MAX 3000A devices are available in a wide range of packages, including
PLCC, PQFP, and TQFP packages. See
Note:
(1)
MAX 3000A devices use CMOS EEPROM cells to implement logic
functions. The user–configurable MAX 3000A architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debugging cycles, and can be
programmed and erased up to 100 times.
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
Table 2. MAX 3000A Speed Grades
Table 3. MAX 3000A Maximum User I/O Pins
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
Device
Device
When the IEEE Std. 1149.1 (JTAG) interface is used for in–system programming or
boundary–scan testing, four I/O pins become JTAG pins.
44–Pin
MAX 3000A Programmable Logic Device Family Data Sheet
PLCC
34
34
v
v
–4
44–Pin
TQFP
34
34
v
–5
100–Pin
TQFP
Speed Grade
66
80
Table
–6
144–Pin
3.
TQFP
Note (1)
116
96
v
v
v
v
v
–7
208–Pin
PQFP
158
172
FineLine
256-Pin
–10
v
v
v
v
v
BGA
161
208
98
3