EPM7064AETC44-7N Altera, EPM7064AETC44-7N Datasheet - Page 25
![IC MAX 7000 CPLD 64 44-TQFP](/photos/6/70/67053/544-44-tqfp_sml.jpg)
EPM7064AETC44-7N
Manufacturer Part Number
EPM7064AETC44-7N
Description
IC MAX 7000 CPLD 64 44-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7064AETC44-7N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
36
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Family Name
MAX 7000A
# Macrocells
64
Number Of Usable Gates
1250
Frequency (max)
166.67MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
4
# I/os (max)
36
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2009
EPM7064AETC44-7N
EPM7064AETC44-7N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7064AETC44-7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 7000A Programmable Logic Device Data Sheet
Open-Drain Output Option
MAX 7000A devices provide an optional open-drain (equivalent to
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (e.g., interrupt and
write enable signals) that can be asserted by any of several devices. This
output can also provide an additional wired-OR plane.
Open-drain output pins on MAX 7000A devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a high
V
. When the open-drain pin is active, it will drive low. When the pin is
IH
inactive, the resistor will pull up the trace to 5.0 V to meet CMOS V
OH
requirements. The open-drain pin will only drive low or tri-state; it will
never drive high. The rise time is dependent on the value of the pull-up
resistor and load impedance. The I
current specification should be
OL
considered when selecting a pull-up resistor.
Programmable Ground Pins
Each unused I/O pin on MAX 7000A devices may be used as an
additional ground pin. In EPM7128A and EPM7256A devices, utilizing
unused I/O pins as additional ground pins requires using the associated
macrocell. In MAX 7000AE devices, this programmable ground feature
does not require the use of the associated macrocell; therefore, the buried
macrocell is still available for user logic.
Slew-Rate Control
The output buffer for each MAX 7000A I/O pin has an adjustable output
slew rate that can be configured for low-noise or high-speed performance.
A faster slew rate provides high-speed transitions for high-performance
systems. However, these fast transitions may introduce noise transients
into the system. A slow slew rate reduces system noise, but adds a
nominal delay of 4 to 5 ns. When the configuration cell is turned off, the
slew rate is set for low-noise performance. Each I/O pin has an individual
EEPROM bit that controls the slew rate, allowing designers to specify the
slew rate on a pin-by-pin basis. The slew rate control affects both the rising
and falling edges of the output signal.
Altera Corporation
25