EPM7064AETC44-7N Altera, EPM7064AETC44-7N Datasheet - Page 50
![IC MAX 7000 CPLD 64 44-TQFP](/photos/6/70/67053/544-44-tqfp_sml.jpg)
EPM7064AETC44-7N
Manufacturer Part Number
EPM7064AETC44-7N
Description
IC MAX 7000 CPLD 64 44-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7064AETC44-7N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
36
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Family Name
MAX 7000A
# Macrocells
64
Number Of Usable Gates
1250
Frequency (max)
166.67MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
4
# I/os (max)
36
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2009
EPM7064AETC44-7N
EPM7064AETC44-7N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7064AETC44-7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 7000A Programmable Logic Device Data Sheet
50
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
Table 28. EPM7128A Internal Timing Parameters (Part 1 of 2)
Input pad and buffer delay
I/O input pad and buffer
delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable
delay
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = on
V
Output buffer enable
delay, slow slew rate = off
V
Output buffer enable
delay, slow slew rate = off
V
Output buffer enable
delay, slow slew rate = on
V
Output buffer disable
delay
Register setup time
Register hold time
Register setup time of fast
input
Register hold time of fast
input
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
= 3.3 V
= 2.5 V
= 3.3 V
Parameter
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
C1 = 5 pF
Conditions
Min
1.9
1.5
0.8
1.7
-6
Max
2.4
0.6
0.6
2.7
2.5
0.7
2.4
0.0
0.4
0.9
5.4
4.0
4.5
9.0
4.0
Min
2.4
2.2
1.1
1.9
-7
Note (1)
Speed Grade
Max
0.7
0.7
3.1
3.2
0.8
3.0
3.0
0.0
0.6
1.1
5.6
4.0
4.5
9.0
4.0
Min
3.1
3.3
1.1
1.9
-10
Max
10.0
0.9
0.9
3.6
4.3
1.1
4.1
4.1
0.0
0.7
1.2
5.7
5.0
5.5
5.0
Altera Corporation
Min
3.8
4.3
1.1
1.9
-12
Max
10.0
1.1
1.1
3.9
5.1
1.3
4.9
4.9
0.0
0.9
1.4
5.9
5.0
5.5
5.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns