EPM2210F324C5N Altera, EPM2210F324C5N Datasheet - Page 11

• Manufacturer Part Number: EPM2210F324C5N
• Description: IC MAX II CPLD 2210 LE 324-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM2210F324C5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of I /o: 272
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 324-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 2210
• Family Name: MAX II
• # Macrocells: 1700
• Frequency (max): 1.8797GHz
• Propagation Delay Time: 11.2ns
• Number Of Logic Blocks/elements: 221
• # I/os (max): 272
• Operating Supply Voltage (typ): 2.5/3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: P0305 - KIT MAX II MICRO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1961; EPM2210F324C5N

Chapter 2: MAX II Architecture
Functional Description
Table 2–1. MAX II Device Resources
Figure 2–2. MAX II Device Floorplan
Note to
(1) The device shown is an EPM570 device. EPM1270 and EPM2210 devices have a similar floorplan with more LABs. For EPM240 devices, the CFM
© October 2008 Altera Corporation
EPM240
EPM570
EPM1270
EPM2210
Note to
(1) The width is the number of LAB columns in length.
and UFM blocks are located on the left side of the device.
Devices
Figure
Table
Logic Array
I/O Blocks
I/O Blocks
I/O Blocks
2 GCLK
2–2:
2–1:
Inputs
Blocks
UFM Blocks
Figure 2–2
1
1
1
1
shows a floorplan of a MAX II device.
(Note 1)
LAB Columns
12
16
20
6
Long LAB Rows
10
4
4
7
LAB Rows
CFM Block
Short LAB Rows
UFM Block
(Width)
3 (3)
3 (5)
3 (7)
—
(1)
Total LABs
127
221
24
57
MAX II Device Handbook
2 GCLK
Inputs
Logic Array
Blocks
2–3