EPM2210F324C5N Altera, EPM2210F324C5N Datasheet - Page 3
![IC MAX II CPLD 2210 LE 324-FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EPM2210F324C5N
Manufacturer Part Number
EPM2210F324C5N
Description
IC MAX II CPLD 2210 LE 324-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM2210F324C5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
2210
Number Of Macrocells
1700
Number Of I /o
272
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
324-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
2210
Family Name
MAX II
# Macrocells
1700
Frequency (max)
1.8797GHz
Propagation Delay Time
11.2ns
Number Of Logic Blocks/elements
221
# I/os (max)
272
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
P0305 - KIT MAX II MICRO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1961
EPM2210F324C5N
EPM2210F324C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM2210F324C5N
Manufacturer:
ALTERA
Quantity:
453
Part Number:
EPM2210F324C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Introduction
Features
© August 2009 Altera Corporation
MII51001-1.9
The MAX
6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128
to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices
offer high I/O counts, fast performance, and reliable fitting versus other CPLD
architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and
enhanced in-system programmability (ISP), MAX II devices are designed to reduce
cost and power while providing programmable solutions for applications such as bus
bridging, I/O expansion, power-on reset (POR) and sequencing control, and device
configuration control.
The MAX II CPLD has the following features:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Low-cost, low-power CPLD
Instant-on, non-volatile architecture
Standby current as low as 25 µA
Provides fast propagation delay and clock-to-output times
Provides four global clocks with two clocks available per logic array block (LAB)
UFM block up to 8 Kbits for non-volatile storage
MultiVolt core enabling external supply voltages to the device of either
3.3 V/2.5 V or 1.8 V
MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels
Bus-friendly architecture including programmable slew rate, drive strength,
bus-hold, and programmable pull-up resistors
Schmitt triggers enabling noise tolerant inputs (programmable per pin)
I/Os are fully compliant with the Peripheral Component Interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V
operation at 66 MHz
Supports hot-socketing
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry
compliant with IEEE Std. 1149.1-1990
ISP circuitry compliant with IEEE Std. 1532
®
II family of instant-on, non-volatile CPLDs is based on a 0.18-µm,
1. Introduction
MAX II Device Handbook