EPM9560ARC208-10 Altera, EPM9560ARC208-10 Datasheet - Page 16

• Manufacturer Part Number: EPM9560ARC208-10
• Description: IC MAX 9000 CPLD 560 208-RQFP
• Manufacturer: Altera
• Series: MAX® 9000r

Specifications of EPM9560ARC208-10

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 35
• Number Of Macrocells: 560
• Number Of Gates: 12000
• Number Of I /o: 153
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-RQFP
• Voltage: 3.3V/5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 35
• Family Name: MAX 9000
• # Macrocells: 560
• Number Of Usable Gates: 12000
• Frequency (max): 144.9MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 35
• # I/os (max): 153
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: RQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2363

MAX 9000 Programmable Logic Device Family Data Sheet
16
Figure 9. MAX 9000 Column-to-IOC Connections
Dedicated Inputs
In addition to the general-purpose I/O pins, MAX 9000 devices have four
dedicated input pins. These dedicated inputs provide low-skew, device-
wide signal distribution to the LABs and IOCs in the device, and are
typically used for global clock, clear, and output enable control signals.
The global control signals can feed the macrocell or IOC clock and clear
inputs, as well as the IOC output enable. The dedicated inputs can also be
used as general-purpose data inputs because they can feed the row
FastTrack Interconnect (see
I/O Cells
Figure 10
device from either the I/O pins that provide general-purpose input
capability or from the four dedicated inputs. The IOCs are located at the
ends of the row and column interconnect channels.
Each IOC is driven by
a 17-to-1 multiplexer.
shows the IOC block diagram. Signals enter the MAX 9000
IOC1
17
Figure 2 on page
Column FastTrack
Interconnect
48
48
48
IOC10
17
7).
Altera Corporation
Each IOC can drive up
to two column
channels.