EPM9560ARC208-10 Altera, EPM9560ARC208-10 Datasheet - Page 35

• Manufacturer Part Number: EPM9560ARC208-10
• Description: IC MAX 9000 CPLD 560 208-RQFP
• Manufacturer: Altera
• Series: MAX® 9000r

Specifications of EPM9560ARC208-10

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 35
• Number Of Macrocells: 560
• Number Of Gates: 12000
• Number Of I /o: 153
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-RQFP
• Voltage: 3.3V/5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 35
• Family Name: MAX 9000
• # Macrocells: 560
• Number Of Usable Gates: 12000
• Frequency (max): 144.9MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 35
• # I/os (max): 153
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: RQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2363

Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
Power
Consumption
Altera Corporation
t
t
t
t
t
t
t
t
Symbol
LOCAL
ROW
COL
DIN_D
DIN_CLK
DIN_CLR
DIN_IOC
DIN_IO
Table 24. Interconnect Delays
These values are specified under the MAX 9000 device recommended operating conditions, shown in
page
See
delays.
This parameter is a guideline that is sample-tested only. It is based on extensive device characterization. This
parameter applies for both global and array clocking as well as both macrocell and I/O cell registers.
Measured with a 16-bit loadable, enabled, up/down counter programmed in each LAB.
The t
The t
or timing analysis is required to determine actual worst-case performance.
Application Note 77 (Understanding MAX 9000 Timing)
ROW ,
27.
LPA
LAB local array delay
FastTrack row delay
FastTrack column delay
Dedicated input data delay
Dedicated input clock delay
Dedicated input clear delay
Dedicated input I/O register
clock delay
Dedicated input I/O register
control delay
parameter must be added to the t
t
COL,
Parameter
and t
IOC
delays are worst-case values for typical applications. Post-compilation timing simulation
The supply power (P) versus frequency (f
be calculated with the following equation:
P = P
The P
and switching frequency, can be calculated using the guidelines given in
Application Note 74 (Evaluating Power for Altera
depends on the switching frequency and the application logic.
The I
I
CCINT
CCINT
INT
IO
(6)
(6)
value, which depends on the device output load characteristics
+ P
= (A
value is calculated with the following equation:
IO
Conditions
= I
f
LOCAL
MAX
CCINT
MAX 9000 Programmable Logic Device Family Data Sheet
MC
parameter for macrocells running in low-power mode
TON
tog
for more information on test conditions for t
V
) + [B
LC
CC
Min
)
+ P
-10
IO
(MC
Max
0.5
0.9
0.9
4.0
2.7
4.5
2.5
5.5
DEV
MAX
Speed Grade
Min
– MC
) for MAX 9000 devices can
-15
Devices). The I
TON
Max
0.5
1.4
1.7
4.5
3.5
5.0
3.5
6.0
)] + (C MC
Min
-20
CCINT
PD1
Max
Table 15 on
0.5
2.0
3.0
5.0
4.0
5.5
4.5
6.5
USED
and t
value
Unit
ns
ns
ns
ns
ns
ns
ns
ns
PD2
.
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