XC9572-15PC44C Xilinx Inc, XC9572-15PC44C Datasheet

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XC9572-15PC44C

Manufacturer Part Number
XC9572-15PC44C
Description
IC CPLD 72 MACROCELL 44-PLCC
Manufacturer
Xilinx Inc
Series
XC9500r

Specifications of XC9572-15PC44C

Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
15.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
72
Number Of Gates
1600
Number Of I /o
34
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
5V
Memory Type
FLASH
Circuit Type
Advanced, FastFLASH™
Current, Supply
65 mA
Function Type
16-Bits
Logic Function
Programmable
Logic Type
CMOS
Number Of Pins
44
Package Type
PLCC-44
Power Requirements
-0.5 to 7 V
Setup Time
8 ns (Min.)
Special Features
Parallel, Tri-State
Temperature, Operating, Range
-40 to +85 °C
Voltage, Supply
5.5 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
122-1171

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DS065 (v4.3) April 3, 2006
Features
DS065 (v4.3)
Product Specification
7.5 ns pin-to-pin logic delays on all pins
f
72 macrocells with 1,600 usable gates
Up to 72 user I/O pins
5V in-system programmable
-
-
Enhanced pin-locking architecture
Flexible 36V18 Function Block
-
-
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
3.3V or 5V I/O capability
Advanced CMOS 5V FastFLASH™ technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP,
and 100-pin TQFP packages
CNT
Endurance of 10,000 program/erase cycles
Program/erase over full commercial voltage and
temperature range
90 product terms drive any or all of 18 macrocells
within Function Block
Global and product term clocks, output enables,
set and reset signals
to 125 MHz
R
0
0
5
XC9572 In-System
Programmable CPLD
Product Specification
Description
The XC9572 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns. See
ture overview.
Power Management
Power dissipation can be reduced in the XC9572 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
Where:
Figure 1
CC
(mA) = MC
MC
MC
MC = Total number of macrocells used
f = Clock frequency (MHz)
(125)
Figure 1: Typical I
(65)
200
100
0
HP
LP
shows a typical calculation for the XC9572 device.
= Macrocells in low-power mode
= Macrocells in high-performance mode
HP
(1.7) + MC
Clock Frequency (MHz)
CC
vs. Frequency for XC9572
LP
50
(0.9) + MC (0.006 mA/MHz) f
Figure 2
for the architec-
DS065_01_110501
100
(160)
(100)
1

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XC9572-15PC44C Summary of contents

Page 1

... Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See ture overview. Power Management Power dissipation can be reduced in the XC9572 by config- uring macrocells to standard or low-power modes of opera- tion. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for ...

Page 2

... –3 Max GND Max GND GND 1.0 MHz V = GND, No load 1.0 MHz XC9572 In-System Programmable CPLD Value –0.5 to 7.0 –0 0.5 CC –0 0.5 CC –65 to +150 +150 Min Max o C 4.75 5. 4.5 5 4.75 5. 4.5 5.5 3.0 3.6 0 0.80 2 0.5 CCINT ...

Page 3

... XC9572 In-System Programmable CPLD AC Characteristics Symbol Parameter T I/O to output valid PD T I/O setup time before GCK SU T I/O hold time after GCK H T GCK to output valid CO (1) f 16-bit counter frequency CNT (2) f Multiple FB internal operating frequency SYSTEM T I/O setup time before p-term clock input ...

Page 4

... T Incremental product term allocator delay PTA T Slew-rate limited delay SLEW Notes multiplied by the span of the function as defined in the XC9500 family data sheet. PTA DS065 (v4.3) Product Specification XC9572 In-System Programmable CPLD XC9572-7 XC9572-10 Min Max Min Max - 2.5 - 3 ...

Page 5

... XC9572-10PQG100C 10 ns XC9572-10TQ100C 10 ns XC9572-10TQG100C 10 ns XC9572-10PC44I 10 ns XC9572-10PCG44I 10 ns XC9572-10PC84I 10 ns XC9572-10PCG84I 10 ns XC9572-10PQ100I 10 ns XC9572-10PQG100I 10 ns XC9572-10TQ100I 10 ns XC9572-10TQG100I 10 ns XC9572-15PC44C 15 ns XC9572-15PCG44C 15 ns XC9572-15PC84C 15 ns XC9572-15PCG84C 15 ns XC9572-15PQ100C 15 ns XC9572-15PQG100C 15 ns XC9572-15TQ100C 15 ns XC9572-15TQG100C 15 ns XC9572-15PC44I XC95xxx TQ144 ...

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