XC2C128-7TQG144I Xilinx Inc, XC2C128-7TQG144I Datasheet - Page 12
![IC CR-II CPLD 128MCELL 144TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XC2C128-7TQG144I
Manufacturer Part Number
XC2C128-7TQG144I
Description
IC CR-II CPLD 128MCELL 144TQFP
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Specifications of XC2C128-7TQG144I
Operating Temperature
-40°C ~ 85°C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
3000
Number Of I /o
100
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Features
JTAG
Voltage
1.8V
Memory Type
CMOS
No. Of Macrocells
128
No. Of I/o's
100
Propagation Delay
5.7ns
Global Clock Setup Time
2.4ns
Frequency
244MHz
Supply Voltage Range
1.7V To 1.9V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
XC2C128 CoolRunner-II CPLD
Pin Descriptions (Continued)
12
Function
Block
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Macro-
cell
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
VQ100 CP132 TQ144
77
78
79
80
81
82
85
86
87
89
-
-
-
-
-
-
C12
B12
A12
C11
C10
A10
B11
A11
C9
C8
A8
B8
B7
-
-
-
120
121
124
125
126
128
112
113
115
116
117
118
119
-
-
-
Bank
I/O
www.xilinx.com
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
-
Pin Descriptions (Continued)
Notes:
1.
2.
Function
Block
GTS = global output enable, GSR = global reset/set, GCK =
global clock, CDRST = clock divide reset, DGE = DataGATE
enable.
GCK, GSR, and GTS pins can also be used for general
purpose I/O.
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Macro-
cell
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
VQ100 CP132 TQ144
53
52
50
49
46
44
43
42
41
-
-
-
-
-
-
-
DS093 (v3.2) March 8, 2007
N14
N13
P14
P12
M11
N11
P10
P11
M8
N8
P9
P8
-
-
-
-
Product Specification
77
76
74
71
70
69
68
64
61
60
59
58
-
-
-
-
Bank
I/O
1
1
1
1
1
1
1
1
1
1
1
1
-
-
-
-
R