XC2C384-10FGG324C Xilinx Inc, XC2C384-10FGG324C Datasheet - Page 8

IC CR-II CPLD 384MCELL 324-FBGA

XC2C384-10FGG324C

Manufacturer Part Number
XC2C384-10FGG324C
Description
IC CR-II CPLD 384MCELL 324-FBGA
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Datasheets

Specifications of XC2C384-10FGG324C

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
9.2ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
24
Number Of Macrocells
384
Number Of Gates
9000
Number Of I /o
240
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
324-FBGA
Features
JTAG
Voltage
1.8V
Memory Type
CMOS
No. Of Macrocells
384
No. Of I/o's
240
Propagation Delay
7.1ns
Global Clock Setup Time
3.3ns
Frequency
125MHz
Supply Voltage Range
1.7V To 1.9V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
XC2C384-10FGG324C
Manufacturer:
XILINX
Quantity:
853
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Manufacturer:
Xilinx Inc
Quantity:
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Manufacturer:
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CoolRunner-II CPLD Family
nally generated DataGATE control logic can be assigned to
this I/O pin with the BUFG=DATA_GATE attribute.
Global Signals
Global signals, clocks (GCK), sets/resets (GSR), and output
enables (GTS), are designed to strongly resemble each
other. This approach enables design software to make the
best utilization of their capabilities. Each global capability is
supplemented by a corresponding product term version.
Figure 7
trees. The pin input is buffered, then drives multiple internal
global signal traces to deliver low skew and reduce loading
delays. GCK, GSR, and GTS can also be used as general
8
shows the common structure of the global signal
Figure 6: DataGATE Architecture (output drivers not shown)
Latch
Latch
To AIM
To AIM
MC16
MC16
MC1
MC2
MC1
MC2
PLA
PLA
DataGATE Assertion Rail
www.xilinx.com
AIM
purpose I/Os if they are not needed as global signals. The
DataGATE assertion rail is also a global signal.
Figure 7: Global Clocks (GCK), Sets/Resets (GSR), and
PLA
PLA
MC16
MC16
MC1
MC2
MC1
MC2
Output Enables (GTS)
To AIM
To AIM
To AIM
DS090 (v3.1) September 11, 2008
Latch
Latch
Latch
DS090_07_101001
Product Specification
DS090_06_111201
R

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