XCR3384XL-12FG324C Xilinx Inc, XCR3384XL-12FG324C Datasheet - Page 3
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XCR3384XL-12FG324C
Manufacturer Part Number
XCR3384XL-12FG324C
Description
IC CPLD 3.3V ZERO PWR 324-FBGA
Manufacturer
Xilinx Inc
Series
CoolRunner XPLA3r
Datasheet
1.XCR3384XL-12PQ208C.pdf
(13 pages)
Specifications of XCR3384XL-12FG324C
Programmable Type
In System Programmable (min 1K program/erase cycles)
Delay Time Tpd(1) Max
10.8ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
24
Number Of Macrocells
384
Number Of Gates
9000
Number Of I /o
220
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
324-FBGA
Features
Programmable
Voltage
3.3V
Memory Type
EEPROM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-
Other names
XCR3384XL12FG324C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCR3384XL-12FG324C
Manufacturer:
XILINX
Quantity:
200
Company:
Part Number:
XCR3384XL-12FG324C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XCR3384XL-12FG324C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
AC Electrical Characteristics Over Recommended Operating Conditions
DS024 (v2.0) March 31, 2006
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
T
T
T
T
T
T
T
T
T
T
T
T
f
T
T
T
T
T
T
SYSTEM
Symbol
APRPW
PD1
PD2
CO
SUF
SU1
SU2
H
WLH
PLH
R
L
CONFIG
INIT
POE
POD
PCO
PAO
(4)
(4)
(4)
Specifications measured with one output switching.
See the CoolRunner XPLA3 family data sheet (
See
These parameters guaranteed by design and/or characterization, not testing.
Typical current draw during configuration is 13 mA at 3.6V.
Output C
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
Figure 4
(4)
(4)
R
L
= 5 pF.
Propagation delay time (single p-term)
Propagation delay time (OR array)
Clock to output (global synchronous pin clock)
Setup time (fast input register)
Setup time (single p-term)
Setup time (OR array)
Hold time
Global Clock pulse width (High or Low)
P-term clock pulse width
Asynchronous preset/reset pulse width (High or Low)
Input rise time
Input fall time
Maximum system frequency
Configuration time
ISP initialization time
P-term OE to output enabled
P-term OE to output disabled
P-term clock to output
P-term set/reset to output valid
for derating.
(5)
Parameter
(6)
DS012
(3)
www.xilinx.com
) for recommended operating conditions.
Min.
2.5
4.3
4.8
3.0
4.5
4.5
0
-
-
-
-
-
-
-
-
-
-
-
-
-7
Max.
135
200
200
7.0
7.5
4.5
9.0
9.0
8.0
9.0
20
20
-
-
-
-
-
-
-
XCR3384XL: 384 Macrocell CPLD
Min.
3.0
5.5
6.5
4.0
6.0
6.0
0
-
-
-
-
-
-
-
-
-
-
-
-
-10
Max.
10.0
10.3
11.0
11.0
11.0
102
200
200
9.0
5.8
20
20
-
-
-
-
-
-
-
Min.
3.0
6.7
7.9
5.0
7.5
7.5
0
-
-
-
-
-
-
-
-
-
-
-
-
-12
(1,2)
Max.
10.8
12.0
13.0
13.0
12.4
13.0
200
200
6.9
20
20
83
-
-
-
-
-
-
-
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
ns
ns
ns
ns
3