ATF1502ASV-20JC44 Atmel, ATF1502ASV-20JC44 Datasheet - Page 16
![IC CPLD 20NS 3.3V 44PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
ATF1502ASV-20JC44
Manufacturer Part Number
ATF1502ASV-20JC44
Description
IC CPLD 20NS 3.3V 44PLCC
Manufacturer
Atmel
Series
ATF1502ASVr
Datasheet
1.ATF1502ASV-15AU44.pdf
(25 pages)
Specifications of ATF1502ASV-20JC44
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
20.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Macrocells
32
Number Of I /o
32
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
ATF1502ASV20JC44
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATF1502ASV-20JC44
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
14. Power-down Mode
16
ATF1502ASV
The ATF1502ASV includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply cur-
rent is reduced to less than 3 mA. During power-down, all output data and internal logic states
are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs that were in a high-Z state at the onset will remain at high-Z. During power-down, all
input signals except the power-down pin are blocked. Input and I/O hold latches remain active to
ensure that pins do not float to indeterminate levels, further reducing system power. The power-
down pin feature is enabled in the logic design file. Designs using the power-down pin may not
use the PD pin logic array input. However, all other PD pin macrocell resources may still be
used, including the buried feedback and foldback product term array inputs.
Table 14-1.
Notes:
Symbol
t
t
t
t
t
t
t
t
t
t
IVDH
GVDH
CVDH
DHIX
DHGX
DHCX
DLIV
DLGV
DLCV
DLOV
1. For slow slew outputs, add t
2. Pin or product term.
Parameter
Valid I, I/O before PD High
Valid OE
Valid Clock
I, I/O Don’t Care after PD High
OE
Clock
PD Low to Valid I, I/O
PD Low to Valid OE
PD Low to Valid Clock
PD Low to Valid Output
Power-down AC Characteristics
(2)
(2)
Don’t Care after PD High
Don’t Care after PD High
(2)
(2)
before PD High
before PD High
(2)
(2)
SSO
.
(1)(2)
Min
15
15
15
-15
Max
25
25
25
1
1
1
1
Min
20
20
20
-20
Max
30
30
30
1
1
1
1
1615J–PLD–01/06
Units
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs