ATF1502ASV-20JC44 Atmel, ATF1502ASV-20JC44 Datasheet - Page 4
![IC CPLD 20NS 3.3V 44PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
ATF1502ASV-20JC44
Manufacturer Part Number
ATF1502ASV-20JC44
Description
IC CPLD 20NS 3.3V 44PLCC
Manufacturer
Atmel
Series
ATF1502ASVr
Datasheet
1.ATF1502ASV-15AU44.pdf
(25 pages)
Specifications of ATF1502ASV-20JC44
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
20.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Macrocells
32
Number Of I /o
32
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
ATF1502ASV20JC44
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATF1502ASV-20JC44
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Figure 1-4.
1.1
1.2
4
Product Terms and Select Mux
OR/XOR/CASCADE Logic
ATF1502ASV
ATF1502ASV Macrocell
the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design
modifications to be made in the field via software.
Each ATF1502ASV macrocell has five product terms. Each product term receives as its inputs
all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as needed to the
macrocell logic gates and control signals. The PTMUX programming is determined by the design
compiler, which selects the optimum macrocell configuration.
The ATF1502ASV’s logic structure is designed to efficiently support all types of logic. Within a
single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR
sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to
as many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions.
One input to the XOR comes from the OR sum term. The other XOR input can be a product term
or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selec-
tion. For registered functions, the fixed levels allow DeMorgan minimization of product terms.
The XOR gate is also used to emulate T- and JK-type flip-flops.
1615J–PLD–01/06