XC9536XV-7CS48C Xilinx Inc, XC9536XV-7CS48C Datasheet
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XC9536XV-7CS48C
Specifications of XC9536XV-7CS48C
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XC9536XV-7CS48C Summary of contents
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... Pin-compatible with 3.3V-core XC9536XL device in the 44-pin VQFP package Description The XC9536XV is a 2.5V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems comprised of two 54V18 Function Blocks, providing 800 usable gates with propagation delays of 5 ns. See Figure 2 overview ...
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... Function block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 200 MHz 200 150 DS053_01_121501 3 JTAG In-System Programming Controller 1 Controller I/O Blocks Figure 2: XC9536XV Architecture www.xilinx.com 54 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells DS053_02_041200 DS053 (v3.0) June 25, 2007 Product Specification ...
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... V CCIO LVTTL 3.3V LVCMOS2 2.5V X25TO18 1.8V The XC9536XV CPLD features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages. DS053 (v3.0) June 25, 2007 Product Specification XC9536XV High-performance CPLD The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer ...
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... XC9536XV High-performance CPLD Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Supply voltage for output drivers CCIO V Input voltage relative to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Junction temperature J Notes: 1. Maximum DC undershoot below GND must be limited to either 0. mA, whichever is easier to achieve. During transitions, the device pins may undershoot to – ...
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... P-term S/R to output valid PAO T GCK pulse width (High or Low) WLH T P-term clock pulse width (High or Low) PLH T Asynchronous preset/reset pulse width (High or Low) APRPW DS053 (v3.0) June 25, 2007 Product Specification XC9536XV High-performance CPLD Test Conditions I = –4 –1 –100 μ 8.0 mA ...
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... XC9536XV High-performance CPLD V TEST R 1 Device Output R 2 Internal Timing Parameters Symbol Buffer Delays T Input buffer delay IN T GCK buffer delay GCK T GSR buffer delay GSR T GTS buffer delay GTS T Output buffer delay OUT T Output buffer enable/disable delay EN Product Term Control Delays ...
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... Notes: 1. Global control pin. XC9536XV Global, JTAG and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS V 2.5V CCINT V 1.8vV/2.5V/3.3V CCIO GND No Connects DS053 (v3.0) June 25, 2007 Product Specification BScan Function Order Block VQ44 40 105 2 41 ...
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... XC9536XV High-performance CPLD Device Part Marking and Ordering Combination Information Device Type Package Speed Operating Range Notes: 1. Due to the small size of chip scale packages, part marking on these packages does not follow the above sample and the complete part number cannot be included in the marking. Part marking on chip scale packages by line: · ...
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... T from 6.5 to 5.9. CGK AOI equation on page 1. Removed -3 device. Changed to Preliminary. Added CC DC Characteristics. Added Part Marking Information to Ordering IH o from 260 to 220 C. Updated Device Part Marking. SOL specification to AC Characteristics. Added IOSTANDARD information. APRPW www.xilinx.com XC9536XV High-performance CPLD Description IL 9 ...