XC9536XV-7CS48C Xilinx Inc, XC9536XV-7CS48C Datasheet - Page 3
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XC9536XV-7CS48C
Manufacturer Part Number
XC9536XV-7CS48C
Description
IC CPLD 2.5V ISP 48-CSP
Manufacturer
Xilinx Inc
Series
XC9500XVr
Specifications of XC9536XV-7CS48C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
2.37 V ~ 2.62 V
Number Of Logic Elements/blocks
2
Number Of Macrocells
36
Number Of Gates
800
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-CSBGA
Voltage
2.5V
Memory Type
FLASH
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of I /o
-
Number Of Logic Elements/cells
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Supported I/O Standards
Table 1: IOSTANDARD Options
The XC9536XV CPLD features both LVCMOS and LVTTL
I/O implementations. See
DS053 (v3.0) June 25, 2007
Product Specification
LVTTL
LVCMOS2
X25TO18
IOSTANDARD
R
V
3.3V
2.5V
1.8V
Table 1
CCIO
for I/O standard voltages.
www.xilinx.com
The LVTTL I/O standard is a general purpose EIA/JEDEC
standard for 3.3V applications that use an LVTTL input
buffer and Push-Pull output buffer. The LVCMOS2 standard
is used in 2.5V applications.
XC9500XV CPLDs are also 1.8V I/O compatible. The
X25TO18 setting is provided for generating 1.8V compatible
outputs from a CPLD normally operating in a 2.5V environ-
ment. The default I/O Standard for pads without IOSTAN-
DARD attributes is LVTTL for XC9500XV devices.
XC9536XV High-performance CPLD
3