ADSP-21375KSWZ-2B Analog Devices Inc, ADSP-21375KSWZ-2B Datasheet - Page 28

• Manufacturer Part Number: ADSP-21375KSWZ-2B
• Description: IC DSP 32BIT 266MHZ 208-MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21375KSWZ-2B

• Package / Case: 208-LQFP
• Interface: DAI, DPI
• Operating Temperature: 0°C ~ 70°C
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (256 kB)
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 21375
• Core Frequency Typ: 266MHz
• Dsp Type: Floating Point
• Mmac: 532
• No. Of Pins: 208
• Interface Type: SPI, UART
• Rohs Compliant: Yes
• Operating Temperature Range: 0°C To +70°C
• Package: 208LQFP EP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 266 MHz
• Ram Size: 64 KB
• Device Million Instructions Per Second: 266 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21371/ADSP-21375
SDRAM Interface Timing
Maximum SDRAM frequency for 1.2 V is 133 MHz SDCLK.
Table 26. SDRAM Interface Timing
1
2
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
For F
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, and SDCKE.
SSDAT
HSDAT
SDCLK
SDCLKH
SDCLKL
DCAD
HCAD
DSDAT
ENSDAT
CCLK
= 133 MHz (SDCLK ratio = 1:2).
DATA Setup Before SDCLK
DATA Hold After SDCLK
SDCLK Period
SDCLK Width High
SDCLK Width Low
Command, ADDR, Data Delay After SDCLK
Command, ADDR, Data Hold After SDCLK
Data Disable After SDCLK
Data Enable After SDCLK
DATA (IN)
DATA(OUT)
CMND ADDR
SDCLK
(OUT)
1
t
SSDAT
Figure 16. SDRAM Interface Timing for 133 MHz SDCLK
Rev. B | Page 28 of 52 | June 2008
2
t
2
DCAD
t
SDCLK
1.2 V, 266 MHz
Min
0.58
2.2
7.5
3
3
1.3
1.6
t
t
ENSDAT
HSDAT
t
t
DCAD
Max
5.3
5.3
HCAD
t
SDCLKL
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
SDCLKH
DSDAT
t
HCAD