ADSP-21375KSWZ-2B Analog Devices Inc, ADSP-21375KSWZ-2B Datasheet - Page 35

• Manufacturer Part Number: ADSP-21375KSWZ-2B
• Description: IC DSP 32BIT 266MHZ 208-MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21375KSWZ-2B

• Package / Case: 208-LQFP
• Interface: DAI, DPI
• Operating Temperature: 0°C ~ 70°C
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (256 kB)
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 21375
• Core Frequency Typ: 266MHz
• Dsp Type: Floating Point
• Mmac: 532
• No. Of Pins: 208
• Interface Type: SPI, UART
• Rohs Compliant: Yes
• Operating Temperature Range: 0°C To +70°C
• Package: 208LQFP EP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 266 MHz
• Ram Size: 64 KB
• Device Million Instructions Per Second: 266 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Input Data Port (IDP)
The timing requirements for the IDP are given in
signals (SCLK, FS, and SDATA) are routed to the DAI_P20–1
pins using the SRU. Therefore, the timing specifications pro-
vided below are valid at the DAI_P20–1 pins.
Table 33. Input Data Port (IDP)
1
Parameter
Timing Requirements
t
t
t
t
t
t
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN
SISFS
SIHFS
SISD
SIHD
IDPCLKW
IDPCLK
or any of the DAI pins.
1
1
1
1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising Edge
SDATA Hold After SCLK Rising Edge
Clock Width
Clock Period
DAI_P20-1
DAI_P20-1
DAI_P20-1
(SDATA)
(SCLK)
(FS)
Table
Rev. B | Page 35 of 52 | June 2008
Figure 21. IDP Master Timing
33. IDP
t
IDPCLKW
t
SISFS
t
SISD
SAMPLE EDGE
t
IDPCLK
t
SIHFS
t
SIHD
1.2 V, 266 MHz
Min
3.8
2.5
2.5
2.5
9
24
Max
ADSP-21371/ADSP-21375
Unit
ns
ns
ns
ns
ns
ns