ADSP-21262SKBCZ200 Analog Devices Inc, ADSP-21262SKBCZ200 Datasheet - Page 4

• Manufacturer Part Number: ADSP-21262SKBCZ200
• Description: IC DSP CTLR 32BIT 136CSPBGA
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21262SKBCZ200

• Interface: DAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 136-CSPBGA
• No. Of Bits: 32 Bit
• Frequency: 200MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: SPI
• No. Of I/o's: 23
• Supply Voltage Range: 1.14V To 1.26V, 3.13V To 3.47V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21262SKBCZ200

ADSP-21262
GENERAL DESCRIPTION
The ADSP-21262 SHARC DSP is a member of the SIMD
SHARC family of DSPs featuring Analog Devices Super Har-
vard Architecture. The ADSP-21262 is source code compatible
with the ADSP-2126x, ADSP-21160, and ADSP-21161 DSPs as
well as with first generation ADSP-2106x SHARC processors in
SISD (single-instruction, single-data) mode. Like other SHARC
DSPs, the ADSP-21262 is a 32-bit/40-bit floating-point proces-
sor optimized for high performance signal processing applica-
tions with its dual-ported on-chip SRAM, mask-programmable
ROM, multiple internal buses to eliminate I/O bottlenecks, and
an innovative digital applications interface.
As shown in the Functional Block Diagram on Page 1, the
ADSP-21262 uses two computational units to deliver a five to
ten times performance increase over previous SHARC proces-
sors on a range of DSP algorithms. Fabricated in a state-of-the-
art, high speed, CMOS process, the ADSP-21262 DSP achieves
an instruction cycle time of 5 ns at 200 MHz or 6.6 ns at 150
MHz. With its SIMD computational hardware, the ADSP-21262
can perform 1200 MFLOPS running at 200 MHz or 900
MFLOPS running at 150 MHz.
Table 1. ADSP-21262 Benchmarks (at 200 MHz)
1
The ADSP-21262 continues SHARC’s industry-leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include 2M bit dual-ported SRAM memory, 4M bit
dual-ported ROM, an I/O processor that supports 22 DMA
channels, six serial ports, an SPI, external parallel bus, and digi-
tal applications interface.
The block diagram of the ADSP-21262
following architectural features:
Table 1
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, with reversal) 61.3 µs
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)
[3×3] × [3×1]
[4×4] × [4×1]
Divide (y/×)
Inverse Square Root
Assumes two files in multichannel SIMD mode.
• Two processing elements, each containing an ALU, multi-
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
plier, shifter, and data register file
transfers between memory and the core at every core pro-
cessor cycle
shows performance benchmarks for the ADSP-21262.
1
1
on Page 1
Speed
(at 200 MHz)
3.3 ns
13.3 ns
30 ns
53.3 ns
20 ns
30 ns
illustrates the
Rev. B | Page 4 of 48 | August 2005
Figure 2
precision clock generator to interface with an I
I
would generate itself. Many other SRU configurations are
possible.
ADSP-21262 FAMILY CORE ARCHITECTURE
The ADSP-21262 is code compatible at the assembly level with
the ADSP-21266, ADSP-2136x, ADSP-2116x, and the first gen-
eration ADSP-2106x SHARC DSPs. The ADSP-21262 shares
architectural features with the ADSP-2126x, ADSP-2136x, and
ADSP-2116x SIMD SHARC family of DSPs, as detailed in the
following sections.
SIMD Computational Engine
The ADSP-21262 contains two computational processing ele-
ments that operate as a single-instruction multiple-data (SIMD)
engine. The processing elements are referred to as PEX and PEY
and each contains an ALU, multiplier, shifter, and register file.
PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing ele-
ments, but each processing element operates on different data.
This architecture is efficient at executing math intensive DSP
algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
2
S DAC with a much lower jitter clock than the serial port
• Three programmable interval timers with PWM genera-
• On-chip dual-ported SRAM (2M bit)
• On-chip dual-ported, mask-programmable ROM
• JTAG test access port
• 8- or 16-bit parallel port that supports interfaces to off-chip
• DMA controller
• Six full-duplex serial ports
• SPI-compatible interface
• Digital applications interface that includes two precision
tion, PWM capture/pulse width measurement, and
external event counter capabilities
(4M bit)
memory peripherals
clock generators (PCG), an input data port (IDP), six serial
ports, eight serial interfaces, a 20-bit synchronous parallel
input port, 10 interrupts, six flag outputs, six flag inputs,
three programmable timers, and a flexible signal routing
unit (SRU)
shows one sample configuration of a SPORT using the
2
S ADC and an