KMSC8122TVT6400V Freescale Semiconductor, KMSC8122TVT6400V Datasheet - Page 3

• Manufacturer Part Number: KMSC8122TVT6400V
• Description: DSP 16BIT QUAD CORE 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of KMSC8122TVT6400V

• Interface: DSI, Ethernet, RS-232
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.10V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
M2-Accessible Multi-
Core Bus (MQBus)
Multi-Core Shared
60x-Compatible
Extended Core
Interface (DSI)
3-Mode Signal
Internal PLL
Multiplexing
System Bus
Direct Slave
Memories
Feature
Each SC140 core is embedded within an extended core that provides the following:
• 224 KB M1 memory that is accessed by the SC140 core with zero wait states.
• Support for atomic accesses to the M1 memory.
• 16 KB instruction cache, 16 ways.
• A four-entry write buffer that frees the SC140 core from waiting for a write access to finish.
• External cache support by asserting the global signal (GBL) when predefined memory banks are accessed.
• Programmable interrupt controller (PIC).
• Local interrupt controller (LIC).
• 475 KB M2 memory (shared memory) working at the core frequency, accessible from the local bus, and
• 4 KB bootstrap ROM.
• A QBus protocol multi-master bus connecting the four SC140 cores to the M2 memory.
• Data bus access of up to 128-bit read and up to 64-bit write.
• Operation at the SC140 core frequency.
• A central efficient round-robin arbiter controlling SC140 core access on the MQBus.
• Atomic operation control of access to M2 memory by the four SC140 cores and the local bus.
• Generates up to 500 MHz core clock and up to 166 MHz bus clocks for the 60x-compatible local and system
• PLL values are determined at reset based on configuration signal values.
• 64/32-bit data and 32-bit address 60x bus.
• Support for multiple-master designs.
• Four-beat burst transfers (eight-beat in 32-bit wide mode).
• Port size of 64, 32, 16, and 8 controlled by the internal memory controller.
• Bus can access external memory expansion or off-device peripherals, or it can enable an external host device to
• Slave support, direct access by an external host to internal resources including the M1 and M2 memories.
• On-device arbitration between up to four master devices.
A 32/64-bit wide slave host interface that operates only as a slave device under the control of an external host
processor.
• 21–25 bit address, 32/64-bit data.
• Direct access by an external host to internal and external resources, including the M1 and the M2 memories as
• Synchronous and asynchronous accesses, with burst capability in the synchronous mode.
• Dual or Single strobe modes.
• Write and read buffers improve host bandwidth.
• Byte enable signals enables 1, 2, 4, and 8 byte write access granularity.
• Sliding window mode enables access with reduced number of address pins.
• Chip ID decoding enables using one
• Broadcast
• Big-endian, little-endian, and munged little-endian support.
• 64-bit DSI, 32-bit system bus.
• 32-bit DSI, 64-bit system bus.
• 32-bit DSI, 32-bit system bus, and Ethernet (MII/RMII).
accessible from all four SC140 cores using the MQBus.
buses and other modules.
access internal resources.
well as external devices on the system bus.
CS
signal enables parallel write to multiple DSPs.
MSC8122 Product Brief, Rev. 6
CS
signal for multiple DSPs.
Description
Features
3