ADSP-2184BST-160 Analog Devices Inc, ADSP-2184BST-160 Datasheet

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... ALU operations, I/O memory transfers, and global interrupt masking for increased flexibility. Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2184 operates with instruction cycle time. Every instruction can execute in a single processor cycle. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...

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... ADSP-218x based evaluation board with PC monitor software plus Assembler, Linker, Simulator and PROM Splitter software. The ADSP-21xx EZ-KIT Lite is a low cost, easy to use hardware platform on which you can quickly get started with your DSP soft- ware design. The EZ-KIT Lite includes the following features: • ...

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... The ADSP-2184 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2184 SPORTs. For additional information on Serial Ports, refer to the ADSP- 2100 Family User’s Manual, Third Edition. ...

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... SPORT configuration determined by the DSP System Control Register. Soft- ware configurable. Memory Interface Pins The ADSP-2184 processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities ...

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... The CLKOUT pin may also be disabled to reduce external power dissipation. Power-Down The ADSP-2184 processor has a low power feature that lets the processor enter a very low power dormant state through hard- ware or software control. Following is a brief list of power-down features. Refer to the ADSP-2100 Family User’s Manual, Third Edition, “ ...

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... ADSP-2184 Idle When the ADSP-2184 is in the Idle Mode, the processor waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs serviced; execution then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA and autobuffer cycle steals still occur ...

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... Clock Signals The ADSP-2184 can be clocked by either a crystal or a TTL- compatible clock signal. The CLKIN input cannot be halted, changed during operation or operated below the specified frequency during normal opera- tion. The only exception is while the processor is in the power- down state. For additional information, refer to Chapter 9, ADSP-2100 Family User’ ...

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... PROGRAM MEMORY ADDRESS RESERVED 8K EXTERNAL Figure 5. Program Memory (Mode Data Memory The ADSP-2184 has 4K 16-bit words of internal data memory. In addition, the ADSP-2184 allows the use of 8K external memory overlays. Figure 6 shows the organization of the data memory. DATA MEMORY ADDRESS 32 MEMORY– ...

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... Internal Memory DMA Port (IDMA Port; Host Memory Mode) The IDMA Port provides an efficient means of communication between a host system and the ADSP-2184. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP’ ...

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... Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers, • Asserting the bus grant (BG) signal, and • Halting program execution Mode is enabled, the ADSP-2184 will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-2184 is performing an external memory access ...

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... These pins have no function except during emulation, and do not require pull-up or pull-down resistors. The traces for these signals between the ADSP-2184 and the connector must be kept as short as pos- sible, no longer than three inches. The following pins are also used by the EZ-ICE: ...

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... EINT within published limits. ELIN Restriction: All memory strobe signals on the ADSP-2184 (RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your target ECLK system must have 10 k pull-up resistors connected when the EZ-ICE is being used. The pull-up resistors are necessary ...

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... Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, PF0–PF7 BR Idle refers to ADSP-2184 state of operation during execution of IDLE instruction. Deasserted pins are driven to either measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 12, 13, 14), 30% are type 2 DD and type 6, and 20% are idle instructions ...

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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2184 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

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... Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). CLKIN CLKOUT * PF(2:0) RESET REV. 0 Min 0.5 t – 0.5 t – CKI t CKIH t CKIL t CKOH t CKH t CKL PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A Figure 9. Clock Signals –15– ADSP-2184 Max Unit 150 ...

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... IFS IFH following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition, for further information on interrupt servicing.) 2 Edge-sensitive interrupts require pulsewidths greater than 10 ns ...

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... asynchronous signal meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on 1 the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships. BGH is asserted when the bus is granted and the processor requires control of the bus to continue. ...

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... ADSP-2184 TIMING PARAMETERS Parameter Memory Read Timing Requirements: RD Low to Data Valid t RDD A0–A13, xMS to Data Valid t AA Data Hold from RD High t RDH Switching Characteristics: RD Pulsewidth t RP CLKOUT High to RD Low t CRD A0–A13, xMS Setup before RD Low t ASR A0–A13, xMS Hold after RD Deasserted ...

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... CLKOUT A0–A13 DMS, PMS, BMS, CMS, IOMS REV. 0 Min 0.5 t – 0.25 t – 0.5 t – 0.25 t – 0.25 t – 0.25 t – 0.75 t – 0.25 t – 0.5 t – WRA WWR ASW CWR WDE Figure 13. Memory Write –19– ADSP-2184 Max Unit 0. DDR ...

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... ADSP-2184 TIMING PARAMETERS Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High to DT Enable SCDE t SCLK High to DT Valid ...

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... Start of Address Latch = IS Low and IAL High. 1 End of Address Latch = IS High or IAL Low. 2 Start of Write or Read = IS Low and IWR Low or IRD Low. 3 IACK IAL IS IAD 15–0 IRD OR IWR REV IKA t IALP t t IASU IAH t IALS Figure 15. IDMA Address Latch –21– ADSP-2184 Min Max Unit ...

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... ADSP-2184 TIMING PARAMETERS Parameter IDMA Write, Short Write Cycle Timing Requirements: IACK Low before Start of Write t IKW Duration of Write IWP t IAD15–0 Data Setup before End of Write IDSU t IAD15–0 Data Hold after End of Write IDH Switching Characteristic: Start of Write to IACK High ...

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... If Write Pulse ends before IACK Low, use specifications Write Pulse ends after IACK Low, use specifications t 3 This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual, Third Edition. 4 IACK IS IWR IAD 15– ...

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... ADSP-2184 TIMING PARAMETERS Parameter IDMA Read, Long Read Cycle Timing Requirements: IACK Low before Start of Read t IKR End of Read after IACK Low t IRK Switching Characteristics: IACK High after Start of Read t IKHR IAD15–0 Data Setup before IACK Low t IKDS t IAD15–0 Data Hold after End of Read ...

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... IAD15–0 Previous Data Valid after Start of Read IRDV NOTES Start of Read = IS Low and IRD Low. 1 End of Read = IS High or IRD High. 2 REV IACK t IKR t IKHR IS t IRP IRD t IRDE PREVIOUS IAD 15–0 DATA t IRDV Figure 19. IDMA Read, Short Read Cycle –25– ADSP-2184 Min Max IKDH t IKDD Unit ...

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... MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL DD MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 12, 13, 14) 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. 3 IDLE REFERS TO ADSP-2184 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V 4 TYPICAL POWER DISSIPATION AT 5. ...

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... CAPACITIVE LOADING Figures 22 and 23 show the capacitive loading characteristics of the ADSP-2184 + 4. 100 150 C – Figure 22. Typical Output Rise Time vs. Load Capacitance, C (at Maximum Ambient Operating Temperature NOMINAL –2 –4 – 100 C – Figure 23. Typical Output Valid Delay or Hold vs. Load Capacitance, C (at Maximum Ambient Operating ...

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... ADSP-2184 ENVIRONMENTAL CONDITIONS Ambient Temperature Rating – (PD ) AMB CASE Case Temperature in C CASE PD = Power Dissipation Thermal Resistance (Case-to-Ambient Thermal Resistance (Junction-to-Ambient Thermal Resistance (Junction-to-Case) JC Package JA LQFP 50 C/W 10k 1k 100 C/W 48 C/W 1 –28– 5.6V 5. 100 0 TEMPERATURE – C Figure 27. Power-Down Supply Current 120 REV ...

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... GND CLKIN 13 14 XTAL 15 VDD 16 CLKOUT GND 17 18 VDD BMS 21 DMS 22 PMS 23 IOMS 24 CMS 25 REV. 0 100-Lead LQFP Package Pinout ADSP-2184 TOP VIEW (Not to Scale) –29– ADSP-2184 75 D15 74 D14 73 D13 72 D12 71 GND 70 D11 69 D10 VDD 66 GND D7/IWR 63 D6/IRD 62 D5/IAL 61 D4/IS 60 GND ...

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... ADSP-2184 The ADSP-2184 package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. ...

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... Ambient Temperature Part Number Range ADSP-2184BST-160 – +85 C *ST = Plastic Thin Quad Flatpack (LQFP). 0.030 (0.75) 0.024 (0.60) TYP 0.020 (0.50) COPLANARITY REV. 0 ORDERING GUIDE Instruction Rate (MHz) 40.0 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 100-Lead Metric Thin Plastic Quad Flatpack (LQFP) (ST-100) 0 ...