ADSP-2184BST-160 Analog Devices Inc, ADSP-2184BST-160 Datasheet - Page 6

• Manufacturer Part Number: ADSP-2184BST-160
• Description: IC DSP CONTROLLER 16BIT 100LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2184BST-160

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 20kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP

ADSP-2184
Idle
When the ADSP-2184 is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction.
In Idle mode IDMA, BDMA and autobuffer cycle steals still
occur.
Slow Idle
The IDLE instruction is enhanced on the ADSP-2184 to let the
processor’s internal clock signal be slowed, further reducing
power consumption. The reduced clock frequency, a program-
mable fraction of the normal clock rate, is specified by a select-
able divisor given in the IDLE instruction. The format of the
instruction is
IDLE (n);
where n = 16, 32, 64 or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2184 will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64
or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-2184, two serial devices, a byte-wide EPROM and optional
external program and data overlay memories (mode selectable).
Programmable wait state generation allows the processor to
connect easily to slow peripheral devices. The ADSP-2184 also
provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode
allows access to the full external data bus, but limits addressing
to a single address bit (A0). Additional system peripherals can
be added in this mode through the use of external hardware to
generate and latch address signals.
–6–
CONTROLLER
INTERFACE
1/2x CLOCK
1/2x CLOCK
SYSTEM
CRYSTAL
CRYSTAL
OR
SERIAL
DEVICE
SERIAL
DEVICE
SERIAL
DEVICE
SERIAL
DEVICE
OR
OR
Figure 2. Basic System Configuration
16
CLKIN
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SCLK0
RFS0
TFS0
DT0
DR0
CLKIN
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SCLK0
RFS0
TFS0
DT0
DR0
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
IAD15-0
FULL MEMORY MODE
XTAL
FL0-2
PF3
MODE C/PF2
MODE B/PF1
MODE A/PF0
XTAL
FL0-2
PF3
MODE C/PF2
MODE B/PF1
MODE A/PF0
HOST MEMORY MODE
IDMA PORT
SPORT1
SPORT0
SPORT1
SPORT0
ADSP-2184
ADSP-2184
ADDR13-0
DATA23-0
PWDACK
DATA23-8
PWDACK
ADDR0
IOMS
BMS
DMS
CMS
PWD
IOMS
PMS
BGH
BMS
PWD
PMS
DMS
CMS
BGH
BG
BR
BR
BG
14
1
24
16
A
D
13-0
23-16
D
A
A
D
D
15-8
10-0
13-0
23-0
23-8
A0-A21
CS
CS
CS
DATA
ADDR
DATA
ADDR
DATA
(PERIPHERALS)
2048 LOCATIONS
PM SEGMENTS
DM SEGMENTS
I/O SPACE
OVERLAY
MEMORY
TWO 8K
TWO 8K
MEMORY
BYTE
REV. 0